MX663DW Ver la hoja de datos (PDF) - MX-COM Inc
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Lista de partido
MX663DW Datasheet PDF : 17 Pages
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Call Progress Decoder
2. Signal List
4
MX663 Preliminary Information
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
XTAL
XTAL/CLOCK
D3
D2
D1
D0
CS
IRQ
ENABLE
VSS
SIGIN
VBIAS
IN+
IN-
AMPOUT
VDD
Type
output
input
output
input
output
input
Power
input
output
input
input
output
Power
Description
Inverted output of the on-chip oscillator.
Input to the on-chip oscillator, for external Xtal circuit or clock.
D3, D2, D1 and D0 is a 4-bit parallel data word output to the µC. The
transmission of data is under the control of the CS input. These 3-
state outputs are held at high impedance when CS is at "1". See
Figure 8
If CS is permanently at "0", D3, D2, D1 and D0 are permanently active.
See Figure 4 and Figure 7.
The chip select pin activates the Data Bus “D0: 3” when held low. A
µC can provide this input to allow the MX663 to reside on a shared
Data Bus. Data transfer sequences are initiated, completed or aborted
by the CS signal. See Figure 8
This output indicates an interrupt condition to the µC by going to a logic
"0". This is a "wire-ORable" output, enabling the connection of up to 8
peripherals to 1 interrupt port on the µC. This pin has a low impedance
pulldown to logic "0" when active and a high-impedance when inactive.
An external pullup resistor is required.
If CS is permanently at "0", the interrupt condition is a logic "0" pulse.
See Figure 4 and Figure 7.
A low level input selects the powersave mode, all circuits are reset and
disabled. D0 - D3 outputs become high impedance. A high level input
enables all circuits.
Negative supply (ground).
Signal input. The signal to this pin should be ac coupled. The dc bias
of this pin is set internally.
Internally generated bias voltage, held at VDD/2 when the device is not
in powersave mode, it should be bypassed to VSS by a capacitor
mounted close to the device pins. In powersave mode this pin is pulled
towards VSS.
Non-inverting input to the on-chip amplifier.
Inverting input to the on-chip amplifier.
Output of the on-chip amplifier, this is internally connected to the input
of the Level Detector.
The positive supply rail. Levels and voltages are dependent upon this
supply. This pin should be bypassed to VSS by a capacitor.
Table 1: Signal List
© 1999 MX-COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480165.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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