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SY69754AL

3.3V, 622Mbps Clock and Data Recovery

Micrel 

Micrel, Inc.

SY69754AL

Pin Description

Inputs

Pin Number Pin Name

2

RDINP

3

RDINN

5

REFCLK

26

CD

32

DIVSEL1

25

DIVSEL2

16

CLKSEL

Outputs

Pin Number

31

Pin Name

LFIN

23

RDOUTN

24

RDOUTP

20

RCLKN

21

RCLKP

18

TCLKP

17

TCLKN

9

PLLSP

10

PLLSN

14

PLLRN

15

PLLRP

Type

Differential

PECL

TTL Input

PECL

Input

TTL Input

TTL Input

Pin Name

Serial Data Input: These built-in line receiver inputs are connected to the

differential receive serial data stream. An internal receive PLL recovers the

embedded clock (RCLK) and data (RDOUT) information.

Reference Clock: This input is used as the reference for the internal frequency

synthesizer and the "training" frequency for the receiver PLL to keep it centered in

the absence of data coming in on the RDIN inputs.

Carrier Detect: This input controls the recovery function of the Receive PLL and

can be driven by the carrier detect output of optical modules or from external

transition detection circuitry. When this input is HIGH, the input data stream

(RDIN) is recovered normally by the Receive PLL. When this input is LOW the

data on the inputs RDIN will be internally forced to a constant LOW, the data

outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced

LOW and the clock recovery PLL forced to look onto the clock frequency

generated from REFCLK.

Divider Select: These inputs select the ratio between the output clock frequency

(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference

Frequency Selection” table.

Clock Select: This input is used to select either the recovered clock of the receiver

PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL =

LOW) to the TCLK outputs.

Type

TTL

Output

Differential

PECL

Differential

PECL

Differential

PECL

Pin Name

Link Fault Indicator: This output indicates the status of the input data stream

RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has

locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN

is within the frequency range of the Receive PLL (1000ppm). LFIN is an

asynchronous output.

Receive Data Output: These ECL 100K outputs represent the recovered data

from the input data stream (RDIN). This recovered data is specified against the

rising edge of RCLK.

Clock Output: These ECL 100K outputs represent the recovered clock used to

sample the recovered data (RDOUT).

Clock Output: These ECL 100K outputs represent either the recovered clock

(CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit

clock of the frequency synthesizer (CLKSEL = LOW).

Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis

PLL.

Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.

August 2007

3

M9999-082107-E

hbwhelp@micrel.com or (408) 955-1690

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