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T14L2M16A

128K X 16 HIGH SPEED CMOS STATIC RAM

Taiwan Memory Technology 

tm TE

CH

Preliminary T14L2M16A

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled, CE = OE = VIL , WE =VIH , LB or/and UB = VIL )

tRC

Address

tAA

tOH

D O U T Previous Data Valid

Data Valid

READ CYCLE 2 ( WE =VIH)

tRC

Address

tAA

CE

tACE

UB / LB

OE

D OUT

tBA

tOE

High-Z

tBLZ tOLZ

tLZ

tOH

tHZ

tBHZ

tOHZ

DON'T CARE

UNDEFINED

Notes (READ CYCLE) :

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to

VOH or VOL levels.

4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device

and from device to device interconnection.

5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not

100% tested.

6. Device is continuously selected with CE =VIL .

TM Technology Inc. reserves the right

P. 7

to change products or specifications without notice.

Publication Date: AUG. 2002

Revision:0.A

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