CX74001(2000) Ver la hoja de datos (PDF) - Conexant Systems
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Lista de partido
CX74001 Datasheet PDF : 16 Pages
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CX74001
Rx ASIC
Pin #
1
2
Name
LNA_CTRL1
PCS_LNAIN
Table 1. CX74001 Pin Assignments and Signal Descriptions (1 of 2)
Description
Digital signal used in conjunction with pin 3 to control LNA gain step.
PCS LNA input pin. High-Q matching network should be used to minimize noise figure, and a
DC blocking capacitor is required.
Equivalent Circuit
3
LNA_CTRL0
4
CELL_LNA_IN
Digital signal used in conjunction with pin 1 to control LNA gain step.
Cellular LNA input pin. High-Q matching network should be used to minimize noise figure, and
a DC blocking capacitor is required.
5
VCC_RF_BIAS
Supply voltage to the RF bias (needed by all LNA/Mixer blocks) . An RF bypass capacitor
should be connected from the pin to ground with minimal trace length.
6
CELL_LNA_EMIT
Ground directly to ground with minimum trace length.
7
CELL/PCS
Digital signal used for band selection: 0 = cellular (800 MHz), 1 = PCS (1900 MHz).
8
FM/CDMA
Digital signal used in cellular band for mode selection: 0 = AMPS, 1 = CDMA.
9
VCO_VCC
Voltage supply to the VCO buffers. A bypass capacitor should be placed close to the device
from pin 9 to ground with minimal trace length.
10
VCO_ON
VCO control signal to turn VCO and PLL buffer ON/OFF during slotted paging modes, thereby
increasing standby time.
11
CELL_TANK–
12
CELL_TANK+
Differential tank cellular band VCO pin. Care should be taken during the layout of the external
–
tank circuit to prevent parasitic oscillations.
+
Differential tank cellular band VCO pin. Care should be taken during the layout of the external
tank circuit to prevent parasitic oscillations.
13
PCS_TANK–
Differential tank PCS band VCO pin. Care should be taken during the layout of the external
tank circuit to prevent parasitic oscillations.
14
PCS_TANK+
Differential tank PCS band VCO pin. Care should be taken during the layout of the external
tank circuit to prevent parasitic oscillations.
15
LOD
Linearity On Demand. It provides the bias control for the mixers, thereby reducing the chip
current consumption at the expense of input IP3.
16
PLL+
Differential buffered VCO output.
Vcc
Vcc
–
+
17
PLL–
Differential buffered VCO output.
18
SIF
19
I–
20
I+
21
Q+
22
Q–
Digital control signal for SIF selection: 1 = SIF, 0 = Normal.
I channel differential output.
I channel differential output.
Q channel differential output.
Q channel differential output.
4
Conexant - Preliminary
101134A
Proprietary Information
October 20, 2000
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