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TDA9852

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled BTSC stereo/SAP

decoder and audio processor

Preliminary specification

TDA9852

handbook, halfpage

OUTL 1

42 OUTR

LDL 2

41 LDR

VIL 3

40 VIR

EOL 4

39 EOR

CAV 5

Vref 6

LIL 7

38 CPS1

37 CPS2

36 LIR

AVL 8

35 AVR

SOL 9

34 SOR

LOL 10

33 LOR

CTW 11 TDA9852 32 CSS

CTS 12

31 CMO

CW 13

30 CER

CS 14

29 CADJ

VEO 15

28 CPH

VEI 16

27 CP2

CNR 17

26 CP1

CM 18

25 VCAP

CDEC 19

24 COMP

GND 20

23 VCC

SDA 21

22 SCL

MHA310

Fig.3 Pin configuration (SDIP-version).

FUNCTIONAL DESCRIPTION

Stereo decoder

INPUT LEVEL ADJUSTMENT

The composite input signal is fed to the input level

adjustment stage. The control range is from

−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress

control 3 of Tables 5 and 6 and the level adjust setting of

Table 21 allows an optimum signal adjustment during the

set alignment. The maximum input signal voltage is

2 V (RMS).

STEREO DECODER

The output signal of the level adjustment stage is coupled

to a low-pass filter which suppresses the baseband noise

above 125 kHz. The composite signal is then fed into a

pilot detector/pilot cancellation circuit and into the MPX

demodulator. The main L + R signal passes a 75 µs fixed

de-emphasis filter and is fed into the dematrix circuit.

The decoded sub-signal L − R is sent to the stereo/SAP

switch. To generate the pilot signal the stereo demodulator

uses a PLL circuit including a ceramic resonator.

The stereo channel separation is adjusted by an automatic

procedure to be performed during set production. For a

detailed description see Section “Adjustment procedure”.

The stereo identification can be read by the I2C-bus

(see Table 2). Two different pilot thresholds

(data STS = 1; STS = 0) can be selected via the I2C-bus

(see Table 19).

SAP DEMODULATOR

The composite signal is fed from the output of the input

level adjustment stage to the SAP demodulator circuit

through a 5fH (fH = horizontal frequency) band-pass filter.

The demodulator level is automatically controlled.

The SAP demodulator includes internal noise and field

strength detectors that mute the SAP output in the event of

insufficient signal conditions. The SAP identification signal

can be read by the I2C-bus (see Table 2).

SWITCH

The stereo/SAP switch feeds either the L − R signal or the

SAP demodulator output signal via the internal dbx noise

reduction circuit to the dematrix/switching circuit. Table 12

shows the different switch modes provided at the output

pins LOR and LOL.

1997 Mar 11

8

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