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82C284

Clock Generator and Ready Interface for 80C286 Processors

Intersil 

82C284

Waveforms

t1

t2

t16

EFI

t19

CLK

t15B

t18

t15A t17

t20

NOTE:

1. The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.

FIGURE 9. CLK AS A FUNCTION OF EFI

t16

CLK

t14

t13

SEE

NOTE t13

t14

RES

t24

t24

RESET

DEPENDS ON STATE

OF PREVIOUS RES

t22

t21

READY

NOTE:

1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.

FIGURE 10. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN, AND SRDY + SRDYEN HIGH

CLK

t6

S1 • S0

PCLK

SRDY + SRDYEN

ARDY + ARDYEN

READY

TS

φ1

φ2

TC

φ1

φ2

t6

t5A

UNDEFINED IF THIS IS

FIRST BUS CYCLE

t11

t5B

t23

t23

t25

t9

t10

NOTE 1

t12

t11

t21

t21

NOTE 2

t26

t12

t22

NOTES:

1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.

2. If SRDY + SRDYEN or ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted until the

falling edge of φ2 of TS.

FIGURE 11. READY AND PCLK TIMING WITH RES HIGH

10

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