XRT8000IP Ver la hoja de datos (PDF) - Exar Corporation
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XRT8000IP Datasheet PDF : 24 Pages
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XRT8000
CR3 Register (Power On State = “00000”)
SEL14~SEL10:
These bits control two parameters:
1.) The frequency multiplier “K” for the PLL1, after
selecting Kx56, Kx64 or DATA mode through register CR1
(1 < K < 32), and
2.) The delay time between the rising edge of the sync
output signal (Pin 2) and the rising edge of the CLK1 or
CLI 2 output signals (See Table 6).
Table 4 provides the settings for SEL14~10 bits to
generate harmonic of 56kHz, 64kHz or 1.2kHz at the
output of PLL1.
SEL14~SEL10
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
K factor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PLL1 Output Frequency (kHz)
Kx56 MODE
56
112
168
224
280
336
392
448
504
560
616
672
728
784
840
896
952
1008
1064
1120
1176
1232
1288
1344
1400
1456
1512
1568
1624
1680
1736
1792
Kx64 MODE
64
128
192
256
320
384
448
512
576
640
704
768
832
896
960
1024
1088
1152
1216
1280
1344
1408
1472
1536
1600
1664
1728
1792
1856
1920
1984
2048
DATA MODE
1.2
2.4
4.8
7.2
9.6
12
14.4
16.8
19.2
21.6
24
26.4
28.8
31.2
33.6
36
38.4
40.8
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
43.2
Note:
This table applies to forward or slave modes only
Table 4. CR3 Register
Rev. 1.11
11
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