AD9857 Ver la hoja de datos (PDF) - Analog Devices

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AD9857

CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

Analog Devices 

AD9857

Parameter

POWER SUPPLY VSCURRENT3 (all power specifications at

VDD = 3.3 V, 25°C, REFCLK = 200 MHz)

Full Operating Conditions

160 MHz Clock (×16)

120 MHz Clock (×12)

Burst Operation (25%)

Single-Tone Mode

Power-Down Mode

Full-Sleep Mode

Temp Test Level Min Typ Max

Unit

25°C

I

25°C

I

25°C

I

25°C

I

25°C

I

25°C

I

25°C

I

540 615

mA

445 515

mA

345 400

mA

395 450

mA

265 310

mA

71

80

mA

8

13.5

mA

1 Wake-up time refers to recovery from full-sleep mode. The longest time required is for the reference clock multiplier PLL to lock up (if it is being used). The wake-up

time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the reference clock multiplier lock can be

determined by observing the signal on the PLL_LOCK pin.

2 SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the reference clock multiplier is used to multiply the external reference frequency, the

SYSCLK frequency is the external frequency multiplied by the reference clock multiplier multiplication factor. If the reference clock multiplier is not used, the SYSCLK

frequency is the same as the external REFCLK frequency.

3 CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, auto power-down between burst On, TxENABLE duty cycle = 25%.

Rev. C| Page 7 of 40

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