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XRD66092

CMOS 750 KSPS, 12-Bit Analog-to-Digital Converter with Serial Logic Interface Port

Exar Corporation 

XRD66092

LINV have internal pull down devices. Please see the simplified

logic circuit Figure 5.

plications above 85°C. Up to 1.6 V is allowed for applications

under 85°C.

MINV or LINV

1MΩ

DQ

latch

EN

CLK

DQ

latch

EN

SDO

Figure 5. MINV, LINV Simplified Logic Circuit

VIN Analog Input

The XRD66L92 has a switched capacitor track and hold input

stage. VIN is sampled at the high to low clock transition. The

Figure 6. shows the equivalent input circuit.

VDD

50Ω

CL

41pF 50Ω

VIN

GND

8pF

CL

VRT + VRB +

1.5pF

CL

2

−

CL at PHASE = 1

Figure 6. Equivalent Input Circuit

Reference Ladder Taps

These taps connect to every sixteenth point along the refer-

ence ladder; R4 is 4/16th up from VRB, R7 is 7/16ths up from

VRB. These taps can be used to alter the transfer curve of the

ADC. The internal interconnect resistance from the pin to the

ladder is less than 3Ω for the even numbered taps, (i.e. R4,R6,

etc.) and is approximately 10Ω for the odd numbered taps.

Altering the transfer curve may be desirable to enhance or re-

duce the probability of codes for certain ranges of VIN. This is

often referred to as probability density function shaping, or histo-

gram shaping. 0.8 V maximum per tap is recommended for ap-

APPLICATION NOTES

VIN signals should not exceed VDD +0.5V or go below GND

–0.5V. All pins have internal protection diodes that will protect

them from short transients (<100µs) outside the supply range.

All GND pins are connected internally through the P– sub-

strate. DC voltage differences between any GND pins will cause

undesirable internal substrate currents.

The power supply (VDD) and reference voltage (VRT & VRB)

pins should be decoupled with 0.1µF and 10µF capacitors to

GND, placed as close to the chip as possible.

The digital outputs should not drive long wires or buses. The

capacitive coupling and reflections will contribute noise to the

conversion.

The reference tap pins can be used to create piecewise-lin-

ear transfer functions. By forcing voltages on these pins, a 7

segment transfer function can be made. See Figure 7.

DAC8

DAC7

V8

VRT

V7

R12

DAC6

DAC5

V6

R9

V5

R8

DAC4

DAC3

DAC2

DAC1

V4 R7 XRD66092

V3

R5

V2

R1

V1

VRB

DAC

MP7228

Only the Ladder detail shown.

Figure 7. A/D with Programmed Ladder Control for

Creating a Piecewise Linear Transfer Function

Rev. 1.00

7

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