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TMC2074-NU

Dual Mode CircLink™ Controller

SMSC -> Microchip 

Dual Mode CircLink™ Controller

Datasheet

NOTE: Address acquisition timing in the CircLink delays about 50 ns (with 20 MHz-XTAL).

The read signal differs depending on the CPU type:

nRWM = H: nDS signal at DIR = H

nRWM = L: nRD signal

NOTE: Refer to the AC timing specifications (in another document) for details (setup time, hold time, etc.).

Compare timing specifications for nEHRD=L and nEHRD=H.

1.6.5 Data Bus Width Selection

(W16/SCM[2]: Pin)

This pin selects the width of the data bus in the peripheral mode; H: 16-bit mode, L: 8-bit mode. In the 16-

bit mode, the LSB address in the CircLink is fixed to 0. In the standalone mode, this pin is the clock-

master-ID input pin SCM[2].

1.6.6 Data Bus Byte Swap

(nSWAP/SCM[3]: Pin)

In peripheral mode, this pin selects the data order at 8-bit access. Although the registers in the CircLink

are defined as 16-bit width, 8-bit access is available, and in this case, the assignment of lower/upper byte

of the register and odd/even number of addresses can be changed. The nSWAP=L assigns the lower byte

to even number address/ upper byte to odd number address, and the nSWAP=H assigns the lower byte to

odd number address /upper byte to even number address. In standalone mode, this pin is the clock master

ID input SCM[3].

1.6.7 Data Strobe Polarity Specification

(nDSINV/CMIERRMD: pin)

In peripheral mode, this pin selects the pin polarity of data strobe (nDS). It is active low with nDSINV = H

and active high with nDSINV = L. In standalone mode, this pin is equivalent to CMIERRMD (bit 12) in

Mode Register. The packet receive stops upon the occurrence of a CMI receive error correction (CMIECC)

with CMIERRMD = H.

Revision 0.1 (03-29-06)

Page 20

DATASHEET

SMSC TMC2074

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