MP8799AE Ver la hoja de datos (PDF) - Exar Corporation

Número de pieza

componentes Descripción

Lista de partido

MP8799AE

Very Low Power, 1 MSPS, 10-Bit Analog-to-Digital Converter with 8-Channel Mux

Exar Corporation 

MP8799

Analog Input Multiplexer

Reference Voltages

The MP8799 includes a 8-Channel analog input multiplexer.

The relationship between the clock, the multiplexer address, the

WR and the output data is shown in Figure 10.

The input/output relationship is a function of VREF:

AIN = VIN – VREF(–)

VREF = VREF(+) – VREF(–)

DATA = 1023 ∗ (AIN/VREF)

A system can increase total gain by reducing VREF.

Clock

Sample N

Old Address

Sample M

New Address

Sample

M+1

tCLKS2

tWR tCLKH2

WR

tAS

tAH

ÉÉÉÉ Address ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

DB0-DB9 N-2 Valid

N-1 Valid

Old Address

N Valid

Old Address

M Valid

New Address

tCLKS2 = tCLKH2 = 0

Figure 10. MUX Address Timing

Digital Interfaces

The logic encodes the outputs of the comparators into a bi-

nary code and latches the data in a D-type flip-flop for output.

The functional equivalent of the MP8799 (Figure 12.) is com-

posed of:

1) Delay stage (tAP) from the clock to the sampling phase

(φS).

2) An ideal analog switch which samples VIN.

3) An ideal A/D which tracks and converts VIN with no

delay.

4) A series of two DFF’s with specified hold (tHLD) and

delay (tDL) times.

tAP, tHLD and tDL are specified in the Electrical Characteristics

table.

A2, A1, A0

WR

MUXEN

(Internal Signal)

tAS

tAH

tWR

tMUXEN1

Figure 11. Analog MUX Timing

φS

VIN

A/D

DQ

DQ

DB9-DB0

tAP

MP8799

CLK

N

VIN

tDL

DB9-DB0

N+1

tHLD

N-1

CLK

N

Figure 12. MP8799 Functional Equivalent

Circuit and Interface Timing

Rev. 3.00

9

Share Link: