AD7721AN Ver la hoja de datos (PDF) - Analog Devices
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AD7721AN Datasheet PDF : 16 Pages
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AD7721
Parallel Mode Only
Mnemonic
CS
RD
WR
DRDY
DVAL/SYNC
SDATA/DB11–
STBY/DB0
Function
Chip Select Logic Input.
Read Logic Input. This digital input is used in conjunction with CS to read data from the device.
Write Logic Input. This digital input is used in conjunction with CS to write data to the control register.
In parallel interface mode, a falling edge on DRDY indicates that new data is available to be read from the
interface. During a synchronization or calibration cycle, DRDY remains high until valid data is available.
The function of this pin is determined by the state of bit DB3 in the control register. Writing a logic zero to
bit DB3 will program this pin to be a DVAL output. Writing a logic one to bit DB3 will program this pin to
be a SYNC input pin.
A rising edge on SYNC starts the synchronization cycle. SYNC must be pulsed low for at least one clock
cycle.
When switching this pin from SYNC mode to DVAL mode, it is important that there are no rising edges on
the pin which could cause resynchronization. For this purpose, an internal pull-up resistor has been included
on this pin. Thus, when the external driver driving this pin in SYNC mode is switched off, the DVAL/SYNC
pin remains high.
These pins are both data outputs and control register inputs. Output data is placed on these pins by taking
RD and CS low. Data on these pins is read into the control register by toggling WR low with CS low. With
RD high, these pins are high impedance.
Control functions such as CAL, UNI and STBY, which are available as pins in serial mode, are available as bits in parallel mode.
Table I lists the contents of the control register onboard the AD7721. This register is written to in parallel mode using the WR pin.
Table I. Function of Control Register Bits
Control
Register
Bit
Function
Logical
State Mode
DB0
DB1
DB2
DB3
DB9
STBY
0
1
CAL
0
1
UNI
0
1
DVAL/SYNC 0
1
0
Normal Operation.
Power-Down (Standby) Mode.
Normal Operation.
Writing a Logic “1” to this bit starts a calibration cycle. Internal logic resets this bit to zero at the end of
calibration.
Unipolar Mode.
Bipolar Mode.
Sets DVAL/SYNC Pin to DVAL Mode.
Sets DVAL/SYNC Pin to SYNC Mode.
This bit is used for testing the AD7721. A logic low MUST be written into this bit for normal
operation.
REV. A
–7–
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