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TRC104

2.4 GHz RF Transceiver

RF Monolithics, Inc 

6.4 DC-Balanced Scrambling

The TRC104 is equipped with a scrambling/descrambling function to improve the DC-balance of a transmitted bit

stream. The implementation is show in Figure 16. This function is enabled by setting the SCR_En bit in

configuration register 0x02 to 1. The scrambling/descramble function is only available in Burst Packet Mode.

T R C 1 0 4 D a ta S c r a m b lin g Im p le m e n ta tio n

X7+ X4+ 1

XO R

SR6

SR4

SR3

SR0

XO R

SC R A M B LED

D A TA O U TPU T

6.4 CRC Error Detection

D A T A IN P U T

A ll 7 s h ift r e g is te r s s e t to 1 b e fo r e e a c h s c r a m b lin g ( D C b a la n c in g ) c a lc u la tio n

Figure 16

The CRC error detection option is enabled by setting the CRC_En bit in configuration register 0x02 to 1. A two-

byte CRC is automatically calculated on the payload field and appended to the end of the transmitted packet. On

the receive side, the CRC is recalculated on the payload field and compared to the received CRC. If the CRC

match fails, the received packet is handled according to the setting of the CRC_ERR bit in configuration register

0x02. Otherwise, a good CRC match generates a flag on the INT pin, and the received CRC is discarded. The

polarity of the INT flag is configured by the LVLINT bit in configuration register 0x17. There is no interrupt

generation for a failed packet. The CRC calculation is based on the CCITT polynomial as shown in Figure 17.

T R C 1 0 4 C R C Im p le m e n ta tio n

X 16 + X 12 + X 5 + 1

D A TA

IN P U T

XO R

S R 15

S R 12

XO R

S R 11

SR5

XO R

SR4

SR0

A ll 1 6 s h ift r e g is te r s s e t to 1 b e fo r e e a c h C R C c a lc u la tio n

7 Serial Interface

Figure 17

The serial interface provides two-wire serial communication between the TRC104 and its host microcontroller, as

shown in Figure 18. All FIFO and configuration parameters are accessible through the serial interface. The FIFO

and configuration data pass through the bidirectional SDAT pin with host microcontroller clocking on the SCLK

pin. The CS pin state selects whether the FIFO (Burst Packet Mode only) or the internal configuration registers

are accessed.

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Page 19 of 33

TRC104 - 08/13/09

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