LTC1401I.(RevA) Ver la hoja de datos (PDF) - Linear Technology
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LTC1401I. Datasheet PDF : 20 Pages
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LTC1401
WU
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range,
unless otherwise noted specifications are at TA = 25°C. VCC = 3V, fSAMPLE = 200kHz, tr = tf = 5ns, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSAMPLE(MAX)
tCONV
tACQ
fCLK
tCLK
tWK(NAP)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Maximum Sampling Frequency
Conversion Time
Acquisition Time
fCLK = 3.2MHz
CLK Frequency
CLK Pulse Width
(Notes 5 and 8)
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV↑ to CLK↑ Setup Time
CONV↑ After Leading CLK↑
CONV Pulse Width
(Note 7)
Time from CLK↑ to Sample Mode
Aperture Delay of Sample-and-Hold
Jitter < 50ps
Minimum Delay Between Conversion
(Note 5)
Delay Time, CLK↑ to DOUT Valid
Delay Time, CLK↑ to DOUT Hi-Z
Time from Previous Data Remains Valid After CLK↑
Minimum Time Between Nap/Sleep Request to Wake Up Request
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
(Notes 5 and 8)
● 200
kHz
●
4.1
µs
315
ns
● 0.1
3.2
MHz
● 60
ns
350
ns
● 60
ns
● 100
ns
●0
ns
● 50
ns
80
ns
45
ns
●
350
550
ns
●
60
120
ns
●
60
120
ns
● 15
50
ns
● 50
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below GND or above VCC, they
will be clamped by internal diodes. This product can handle input currents
greater than 40mA without latch-up if the pin is driven below GND or
above VCC.
Note 4: When these pin voltages are taken below GND, they will be clamped
by internal diodes. This product can handle input currents greater than 40mA
without latch-up if the pin is driven below GND. These pins are not clamped
to VCC.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 120ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
Note 8: If this timing specification is not met, the device may not respond
to a request for a conversion. To recover from this condition a NAP
request is required.
1401fa
4
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