TZA3033T Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Lista de partido
TZA3033T Datasheet PDF : 16 Pages
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Philips Semiconductors
SDH/SONET STM1/OC3 transimpedance amplifier
Objective specification
TZA3033
Pad centre locations
SYMBOL
DREF
TESTA
GND
GND
IPhoto
TESTB
GND
GND
GND
GND
OUT
OUTQ
VCC
VCC
AGC
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COORDINATES(1)
x
y
95
881
95
735
95
618
95
473
95
285
95
147
215
95
360
95
549
95
691
95
785
501
785
641
567
1 055
424
1 055
259
1 055
Note
1. All coordinates (µm) are measured with respect to the
bottom left-hand corner of the die.
FUNCTIONAL DESCRIPTION
The TZA3033 is a transimpedance amplifier intended for
use in fibre optic links for signal recovery in STM1/OC3
applications. It amplifies the current generated by a photo
detector (PIN diode or avalanche photodiode) and
transforms it into a differential output voltage. The most
important characteristics of the TZA3033 are high receiver
sensitivity and wide dynamic range.
High receiver sensitivity is achieved by minimizing noise in
the transimpedance amplifier.
The signal current generated by a PIN diode can vary
between 0.25 µA to 1.6 mA (peak-to-peak value).
An AGC loop (see Fig.1) is implemented to make it
possible to handle such a wide dynamic range.
The AGC loop increases the dynamic range of the
receiver by reducing the feedback resistance of the
preamplifier. The AGC loop hold capacitor is integrated
on-chip, so an external capacitor is not needed for AGC.
The AGC voltage can be monitored at pad 15 on the naked
die (TZA3033U). Pad 15 is not bonded in the packaged
device (TZA3033T). This pad can be left unconnected
during normal operation. It can also be used to force an
external AGC voltage. If pad 15 (AGC) is connected to
VCC, the internal AGC loop is disabled and the receiver
gain is at a maximum. The maximum input current is then
about 10 µA.
A differential amplifier converts the output of the
preamplifier to a differential voltage. The data output circuit
is given in Fig.4.
The logic level symbol definitions are shown in Fig.5.
1998 Jul 08
5
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