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U5020M Ver la hoja de datos (PDF) - Temic Semiconductors

Número de pieza
componentes Descripción
Lista de partido
U5020M
Temic
Temic Semiconductors Temic
U5020M Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
U5020M
Pin Description
TM 1
TM 2
Wake-up 3
Wake-up 4
Wake-up 5
Wake-up 6
Wake-up 7
Wake-up 8
16 ts
15 Osc
14 GND
13 VDD
12 Mode
11 Trig
10 Reset
95 10635
9 Ena
Figure 2. Pin connections
Pin
1
2
3 to 8
9
10
11
12
13
14
15
16
Symbol
Function
TM Test must not be connected
TM Test must be connected to GND
Wake-up Wake-up inputs (pull-down
resistor)
There are six digitally debounced
wake-up inputs. During the long
trigger mode each signal slope at
the inputs initiates a reset pulse at
Pin 10.
Ena Enable output (push-pull)
It is used for the control of periph-
eral components. It is activated
after the processor triggers three
times correctly.
Reset
Reset output (open drain)
Resets the processor in the case of
a trigger error or if a wake-up
pulse occurs during the long
watchdog period.
Trig Trigger input (pull-up resistor)
It is connected to the microproces-
sor’s trigger signal.
Mode
Mode input (pull-up resistor)
The processor’s mode signal initi-
ates the switchover between the
long and the short watchdog time.
VDD Supply voltage
GND Ground, reference voltage
Osc RC oscillator
ts Time switch input
Programming pin to select differ-
ent time durations for the long
watchdog time.
Functional Description
Supply, Pin 13
" The U5020M requires a stabilized supply voltage
VDD = 5 V 5% to comply with its electrical
characteristic.
An external buffer capacitor of C = 10 nF may be
connected between Pin 13 and GND.
RC-Oscillator, Pin 15
The clock frequency, f, can be adjusted with the
components R1 and C1 according to the formula:
+f
1
t
+ ) ) where t 1.35 1.57 R1 (C1 0.01)
R1 in kW, C1 in nF and t in ms
The clock frequency determines all time periods of the
logic part as shown in the last section of the data sheet
(timing). With an appropriate selection of components,
the clock frequency, f, is nearly independent of the supply
" " voltage as shown in figure 3. Frequency tolerance
Dfmax = 10% with R1 1%, C1 = 5%.
2 (8)
TELEFUNKEN Semiconductors
Preliminary Information
Rev. A3, 27-Feb-97

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