CMX639 Ver la hoja de datos (PDF) - MX-COM Inc
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CMX639 Datasheet PDF : 12 Pages
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Consumer/Commercial CVSD Digital Voice CODEC
4
2 Signal List
CMX639 Preliminary Information
P6
22-pin
PDIP
1
2
3
E2
24-pin
TSSOP
1
2
3
4
D4
16-pin
SOIC
1
2
Signal Name
Xtal/Clock
N/C
Xtal
N/C
4
5
3
Encoder Data
Clock
5
6
4
Encoder Output
6
7
Not
present Encoder Force Idle
7
8
8
9
5
Data Enable
N/C
9
10
6
Bias
10
11
7
Encoder Input
11
12
12
13
8
VSS
N/C
13
14
9
Decoder Output
14
15
N/C
15
16
10
Powersave
17
N/C
16
18
Not
present Decoder Force Idle
17
19
11 Decoder Input
18
20
12
Decoder Data
Clock
19
21
13 Algorithm
20
22
14
Clock Mode 2
21
23
15
Clock Mode 1
22
24
16
VDD
Type
Description
input
output
input/
output
output
input
input
input
power
output
input
input
input
input/
output
input
input
input
power
Input to the clock oscillator inverter. A 1.024MHz Xtal input or
externally derived clock is injected here. See Table 3 and Figure 3.
No Connection
The 1.024 MHz output of the clock oscillator inverter.
No Connection
A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependent upon Clock Mode 1, 2 inputs
and Xtal frequency (see Table 3). Note: No internal pull-up is
provided.
The encoder digital output. This is a three-state output whose
condition is set by the Data Enable and Powersave inputs. See
Table 2.
When this pin is at a logical '0' the encoder is forced to an idle
state and the encoder digital output is 0101…, a perfect idle
pattern. When this pin is a logical '1' the encoder encodes as
normal. Internal 1MΩ pull-up.
Data is made available at the encoder output pin by control of this
input. See Encoder Output pin. Internal 1 MΩ pull-up.
No Connection
Normally at VDD/2 bias, this pin should be externally decoupled by
capacitor C4. Internally pulled to VSS when Powersave is a logical
'0'.
The analog signal input. Internally biased at VDD/2, this input
requires an external coupling capacitor. The source impedance
driving the coupling capacitor should be less than 1kΩ. A lower
driving source impedance will reduce encoder output channel
noise levels. See Figure 2.
Negative Supply
No Connection
The recovered analog signal is output at this pin. It is the buffered
output of a lowpass filter and requires external components. During
'Powersave' this output is open circuit.
No Connection
A logic '0' at this pin puts most parts of the codec into a quiescent
non-operational state. When at a logical '1', the codec operates
normally. Internal 1 MΩ pull-up.
No Connection
A logic '0' at this pin gates a 0101... pattern internally to the
decoder so that the Decoder Output goes to VDD/2. When this pin
is a logical '1' the decoder operates as normal. Internal 1MΩ pull-
up.
The received digital signal input. Internal 1 MΩ pull-up.
A logic I/O port. External decode clock input or internal data clock
output, dependent upon Clock Mode 1 and 2 inputs. See Table 3.
Note: No internal pull-up is provided.
A logic '1' at this pin sets this device for a 3-bit companding
algorithm. A logical '0' sets a 4-bit companding algorithm. Internal 1
MΩ pull-up.
Clock rates refer to f = 1024MHz Xtal/Clock input. During internal
operation the data clock frequencies are available at the ports for
external circuit synchronization. Independent or common data rate
inputs to Encode and Decode data clock ports may be employed in
the External Clocks mode. Internal 1MΩ pull-ups. See Table 3.
Positive Supply. A single 3.0V to 5.5V supply is required.
Table 1: Signal List
2000 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480209.006
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All Trademarks and service marks are held by their respective companies.
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