SM8750AV Ver la hoja de datos (PDF) - Nippon Precision Circuits

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SM8750AV

Data Jitter Measurement IC

Nippon Precision Circuits  

BLOCK DIAGRAM

SM8750AV

VDD

47k

CALMON

RDCLK

LIMIT

SENB

DATA START VDD TVOUT

Phase comparator

Automatic regulation

controller

to each block

Serial interface

Charge pump

output buffer

(phase difference to

voltage converter)

Duty correction

Delay correction

VREF2

RCP

33k

RDUTY

22k

RDATAF

39k

SCLK SDATA GND

RDATAR

39k

PIN DESCRIPTION

Number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Name

STA RT

D ATA

CALMON

RDCLK

LIMIT

SENB

SCLK

S DATA

GND

R D ATA R

R D ATA F

RDUTY

RCP

VREF2

TVOUT

VDD

I/O

Description

I

Measurement start control. Phase difference to voltage conversion starts on the falling edge.

I

Tw o-valued signal input

O

Internal calibration state signal monitor output. N-channel open drain. Active when calibrated.

I

PLL clock input

I

TVOUT output voltage-limit control voltage input

I

Serial interface: enable signal input

I

Serial interface: clock signal input

I/O Serial interface: data signal input/acknowledge signal output. N-channel open drain.

–

Ground

O

D ATA rising edge: delay adjust circuit reference-current setting resistor connection

O

D ATA falling edge: delay adjust circuit reference-current setting resistor connection

O

RDCLK duty adjust circuit reference-current setting resistor connection

O

Phase difference to voltage converter coefficient reference-current setting resistor connection

I

2V reference voltage input

O

Phase difference to voltage converter output

–

5V supply

NIPPON PRECISION CIRCUITS—2

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