UPA1707 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPA1707

SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE

NEC => Renesas Technology 

µ PA1707

ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN. TYP. MAX. UNIT

Zero Gate Voltage Drain Current

Gate Leakage Current

IDSS

VDS = 30 V, VGS = 0 V

IGSS

VGS = ±20 V, VDS = 0 V

10

µA

±10 µA

Gate Cut-off Voltage

VGS(off) VDS = 10 V, ID = 1 mA

1.5 2.0 2.5

V

Forward Transfer Admittance

Drain to Source On-state Resistance

| yfs |

RDS(on)1

RDS(on)2

RDS(on)3

VDS = 10 V, ID = 5.0 A

VGS = 10 V, ID = 5.0 A

VGS = 4.5 V, ID = 5.0 A

VGS = 4.0 V, ID = 5.0 A

5.0 13

S

10.0 13.5 mΩ

12.5 18

mΩ

14.0 21

mΩ

Input Capacitance

Ciss

VDS = 10 V

1400

pF

Output Capacitance

Reverse Transfer Capacitance

Turn-on Delay Time

Coss

Crss

td(on)

VGS = 0 V

f = 1 MHz

ID = 5.0 A

450

pF

180

pF

20

ns

Rise Time

tr

VGS(on) = 10 V

185

ns

Turn-off Delay Time

Fall Time

td(off)

tf

VDD = 15 V

RG = 10 Ω

65

ns

40

ns

Total Gate Charge

Gate to Source Charge

QG

ID = 10 A

QGS

VDD = 24 V

26

nC

4.2

nC

Gate to Drain Charge

QGD

VGS = 10 V

6.5

nC

Body Diode Forward Voltage

VF(S-D) IF = 10 A, VGS = 0 V

0.8

V

Reverse Recovery Time

Reverse Recovery Charge

trr

IF = 10 A, VGS = 0 V

Qrr

di/dt = 100 A/ µs

30

ns

25

nC

TEST CIRCUIT 1 SWITCHING TIME

D.U.T.

RG

PG.

VGS

0

τ

τ = 1 µs

Duty Cycle ≤ 1%

RL

VGS

VGS

Wave Form

0 10%

VGS(on) 90%

VDD

ID

90%

ID

ID

0 10%

Wave Form

90%

10%

td(on) tr td(off) tf

ton

toff

TEST CIRCUIT 2 GATE CHARGE

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet G13084EJ3V0DS

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