ARX2412 Ver la hoja de datos (PDF) - Aeroflex Corporation
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ARX2412 Datasheet PDF : 7 Pages
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occur going from a logic "1" to logic "0". This signal
transitions at the same time as Valid Word. Upon
detecting a Valid Word output, the user subsystem
must respond with a signal called System
Acknowledge (SACK). A high to low input to the
converter will set both Valid Word and VU INT (if
occurred) to their original high states. These two
outputs are then ready to analyze the next received
20 bit word. At the same time, SACK will enable the
output 3-state buffer for data readout on the 16
parallel data lines. The user subsystem has up to
20µsec to process the data before the next 20 bit
word is ready to be latched in the output buffer. A
return to the high state on SACK will cause the
3-state output buffer to return to the high impedance
state, completing the conversion of one 20 bit word.
The command sync clear input signal is required to
initialize the converter internal logic, set by
detection of command or status sync. It also resets
Valid Word logic. This input signal must be applied
each time a receiver sync type transitions, low to
high, occurs but must not occur until the Valid Word
transitions high to low. Under certain
circumstances, valid address transition may not
occur after a valid sync field is recognized.
ENCODER OPERATION
In the encode mode of operation (Figure 3), the
converter normally provides logic highs (off mode)
on Tx DATA and Tx DATA. These two signal lines
provide output data in complementary serial phase
modulated format to the MIL-STD-1553 transceiver
during a transmission. To effect a transmission from
the converter, the sequence of events is to first load
16 bit parallel data into the 3-state input buffer. This
is achieved by the presentation of an input pulse of
logic zero on the Output Select (OSEL) line. Data to
the converter must be stable when the OSEL
occurs. When the XMTR busy signal goes from low
to high, the OSEL may be activated to load the next
16 bit word in preparation for transmission.
Next, the user subsystem must bring the Encoder
Enable line high to initiate a transmission. Encoder
Enable can be conveniently triggered from the
leading or trailing edge of OSEL but must remain
high for 1.0µsec after the trailing edge of OSEL.
If the Encoder Enable line is allowed to remain high,
successive transmissions will result. The transmitter
busy line will go high for 16µsec every time a 20 bit
word is processed through the internal Encoder.
Transmitter Busy indicates to the user subsystem
that control logic is shifting data from the parallel to
serial data buffer to the bi-phase encoder during a
transmit cycle. To terminate a transmission, the
Encoder Enable line must be brought low on or
before the high to low transition of the current
transmitter busy signal.
The remaining signal that is required to make the
converter encoder operate properly is the Sync
Select input signal. Sync Select is an input from the
user subsystem for the purpose of setting the
appropriate sync field polarity to correspond with
the word to be transmitted. A high on this line will
create a command or status sync field, and a low
will result in a data sync field. Initially it should be
set to a Logic "1" before the encoder enable line is
set high, and remain high no later than the high to
low transition of the transmitter busy signal.
Appplication and Operation
Information
General
LOGIC COMPATIBILITY
Direct logic compatibility exists with transceiver
types which have logical low receiver outputs at
times when the bus is not active, such as Models
ARX3402/4402 and ARX3411/4411. Use with
logical high receiver output devices, such as
Aeroflex Models ARX3231/3232 or ARX3404/4404
will necessitate utilization of inverters between
transceiver RX outputs and Model ARX2412 RX
inputs.
POWER ON CLEAR (POC)
A low on this input line resets all internal registers
and initializes the Manchester Converter for
transmission of complete messages.
DATA I/O (DB0-DB15)
The 16 bits of input and output are three state lines.
Impedance of the receiver section latches is high
during transmit cycle. Latched data can be retained
for up to 20µsec. during input of next data word.
TERMINAL ADDRESS LINES (B0-B4)
Addressing the 5 bit address lines is done by hard
wiring. Internal pull up resistors allow logic "1" lines
to be open circuited. Logic "0" lines must be tied to
ground. When a valid command word incorporating
the proper address is received at the input it will
cause VU INT to go low.
Aeroflex Circuit Technology
3
SCD2412 REV C 10/19/98 Plainview NY (516) 694-6700
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