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LTC1063CS

DC Accurate, Clock-Tunable 5th Order Butterworth Lowpass Filter

Linear Technology 

LTC1063

PI FU CTIO S

filter’s DC output offset (Figure 1). RIN should, however, be

limited to a maximum value (Table 1), otherwise the filter’s

passband flatness will be affected. Refer to the Applica-

tions Information section for more details.

VIN

RIN 1

8

2

V– 3

LTC1063

7 VOUT

6 V+

4

5 fCLK

Figure 1.

1063 F01

Table 1. RIN(MAX) vs Clock and Power Supply

fCLK = 4MHz

fCLK = 3MHz

fCLK = 2MHz

fCLK = 1MHz

fCLK = 500kHz

fCLK = 100kHz

VS = ±7.5V

2.2k

3.4k

5.5k

11k

24k

120k

RIN(MAX)

VS = ±5V

–

2.9k

5k

11k

23k

120k

VS = ±2.5V

–

–

2.7k

9.2k

21k

110k

Output Pin (Pin 7, N Package)

Pin 7 is the filter output. This pin can typically source over

20mA and sink 2mA. Pin 7 should not drive long coax

cables, otherwise the filter’s total harmonic distortion will

degrade.

Clock Input Pin (Pin 5, N Package)

An external clock when applied to pin 5 tunes the filter

cutoff frequency. The clock-to-cutoff frequency ratio is

100:1. The high (VHIGH) and low (VLOW) clock logic

threshold levels are illustrated in Table 2. Square wave

clocks with duty cycles between 30% and 50% are strongly

recommended. Sinewave clocks are not recommended.

Table 2. Clock Pin Threshold Levels

POWER SUPPLY

VS = ±2.5V

VS = ±5V

VS = ±7.5V

VS = ±8V

VS = 5V, 0V

VS = 12, 0V

VS =15V, 0V

VHIGH

1.5V

3V

4.5V

4.8V

4V

9.6V

12V

VLOW

0.5V

1V

1.5V

1.6V

3V

7.2V

9V

Clock Output Pin (Pin 4, N Package)

Any external clock applied to the clock input pin appears

at the clock output pin. The duty cycle of the clock output

equals the duty cycle of the external clock applied to the

clock input pin. The clock output pin swings to the power

supply rails. When the LTC1063 is used in a self-clocking

mode, the clock of the internal oscillator appears at the

clock output pin with a 30% duty cycle. The clock output

pin can be used to drive other LTC1063s or other ICs. The

maximum capacitance, CL(MAX), the clock output pin can

drive is illustrated in Figure 3.

200

180 VS = ±2.5V

160

TA = 25°C

140

120

100 VS = ±5V

80 VS = ±7.5V

60

40

20

0

1

2

3 4 5 6 7 8 9 10

CLOCK FREQUENCY (MHz)

1063 F03

Figure 3. Maximum Load Capacitance at the Clock Output Pin

TEST CIRCUIT

+

LT1022

VIN

1

2

8

7

50k

–

50k

3 LTC1063 6

V+

V–

4

5

0.1µF

20pF

VOUT

0.1µF

CLOCK IN

1063 TC01

Figure 2. Test Circuit for THD

7

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