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LTC1063MJ8

DC Accurate, Clock-Tunable 5th Order Butterworth Lowpass Filter

Linear Technology 

LTC1063

APPLICATI S I FOR ATIO

0.80

0.75

fCLK = K/RC

C = 10pF

TA = 70°C

0.70

0.65

0.60

VS = ±7.5V

0.55

VS = ±5V

0.50

0.45

0.40

0.5

VS = ±2.5V

1.0 1.5 2.0 2.5 3.0

CLOCK FREQUENCY (MHz)

1063 F06

Figure 7. fCLK vs K

A 4pF parasitic capacitance is assumed in parallel with the

external 10pF capacitor. A ±1% clock frequency variation

from device to device can be expected. The 2MHz clock

frequency designed above will typically drift to 1.74MHz at

70°C (Figure 7).

The internal clock of the LTC1063 can be overridden by an

external clock provided that the external clock source can

drive the timing capacitor, C, which is connected from the

clock input pin to ground.

Output Offset

The DC output offset of the LTC1063 is trimmed to

typically less than ±1mV . The trimming is done at VS =

±5V. To obtain optimum DC offset performance, appropri-

ate PC layout techniques should be used and the filter IC

should be soldered to the PC board. A socket will degrade

the output DC offset by typically 1mV. The output DC offset

is sensitive to the coupling of the clock output pin 4 (N

package) to the negative power supply pin 3 (N package).

The negative supply pin should be well decoupled. When

the surface mount package is used, all the unused pins

should be grounded.

When the power supplies are fixed, the output DC offset

should not change by more than ±100µV over 10Hz to

1MHz clock frequency variation. When the filter clock

frequency is fixed, the output DC offset will typically

change by – 4mV (2mV) when the power supply varies

from ±5V to ±7.5V (±2.5V). See Typical Performance

Characteristics.

Common-Mode Rejection Ratio

The common-mode rejection ratio is defined as the change

of the output DC offset with respect to the DC change of the

input voltage applied to the filter.

CMRR = 20log (∆VOS OUT/∆VIN)(dB)

Table 3 illustrates the common-mode rejection for three

power supplies and three temperatures. The common-

mode rejection improves if the output offset is adjusted to

approximately 0V. The output offset can be adjusted via

pin 8 (N package) (see Typical Applications).

Table 3. CMRR Data, fCLK = 100kHz

POWER SUPPLY ∆VIN – 40°C 25°C 85°C

25°C

(VOS Nulled)

± 2.5V

±1.8V 76dB 78dB 76dB

85dB

± 5V

±4V 74dB 79dB 75dB

82dB

± 7.5V

±6V 70dB 72dB 74dB

76dB

The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for

VS = ±2.5V, ±5V, ±7.5V respectively.

Clock Feedthrough

Clock feedthrough is defined as the RMS value of the clock

frequency and its harmonics which are present at the

filter’s output pin. The clock feedthrough is tested with the

filter input grounded and it depends on the quality of the

PC board layout and power supply decoupling. Any para-

sitic switching transients, during the rise and fall of the

incoming clock, are not part of the clock feedthrough

specifications; their amplitude strongly depends on scope

probing techniques as well as ground quality and power

supply bypassing. For a power supply VS = ±5V, the clock

feedthrough of the LTC1063 is 50µVRMS; for VS = ±7.5V,

the clock feedthrough approaches 75µVRMS. Figure 8

shows a typical scope photo of the LTC1063 output pin

when the input pin is grounded. The filter cutoff frequency

was 1kHz, while scope bandwidth was chosen to be 1MHz

such as switching transients above the 100kHz clock

frequency will show.

Wideband Noise

The wideband noise of the filter is the RMS value of the

device’s output noise spectral density. The wideband

noise data is used to determine the operating signal-to-

9

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