UPC1934 Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPC1934 Datasheet PDF : 20 Pages
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µ PC1934
3.5 ON/OFF Control
The ON/OFF control method of the output oscillation is to input the ON/OFF signal from ON as shown in Figure 3-3.
The PWM converter can be turned ON/OFF by controlling the level of the DTC pin. However, it is necessary to keep the
level of the FB output high so that the timer latch does not start when the PWM converter is OFF. In this circuit example,
the FB output level is controlled by controlling the level of the II pin.
Figure 3-3 ON/OFF Control
VO
VREF
R1
R5
Q3
R2
R6
FB
II
–
SCP comparator
(common to each channel) DLY
+
+
IN 0.3 V
Error
amplifier
–
Q
0.63 V
CDLY
VREF
To output stage
–
–
Q2
R3
C1
+
PWM
comparator
DTC
ON
Q1
R4
Oscillation section
(common to each channel)
(1) When ON is high: OFF status
Q1: ON → Q2: ON → DTC pin: High level → Output duty of PWM comparator: 0 %
Q3: ON → II pin: Low level → FB output: High level → SCP comparator output: High level → Q is ON. → Timer latch stops.
(2) When ON3 is low: ON status
Q1: OFF → Q2 is OFF. → C1 is charged in the sequence of [VREF → C1 → R4] → DTC pin voltage drops. → Soft start
Q3: OFF → II pin: High level → FB output: Low level → SCP comparator output: Low level → Q: OFF
→ Charging CDLY starts (timer latch start).
Caution Keep the high-level voltage of the DTC pin at 1.6 V or higher and the low-level voltage of the II pin
within (R6/(R5+R6))•VREF. The maximum voltage that is applied to the II pin must be equal to or lower
than VREF.
3.6 Notes on Actual Pattern Wiring
When actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related
grounds, and make sure that they do not share impedances as far as possible. In addition, make sure the high-frequency
impedance is lowered using capacitors and other components to prevent noise input to the VREF pin.
14
Data Sheet G13567EJ3V0DS00
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