LTC1065 Ver la hoja de datos (PDF) - Linear Technology
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LTC1065 Datasheet PDF : 16 Pages
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APPLICATI S I FOR ATIO
4
C = 200pF
3
TA = –40°C
2
VS = ±2.5V
VS = ±5V
1
VS = ±7.5V
0
TA = 85°C
–1
–2
VS = ±7.5V
–3
VS = ±2.5V
VS = ±5V
–4
0
100 200 300 400 500
CLOCK FREQUENCY (kHz)
1065 F05
Figure 5. fCLK vs Temperature
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.5
fCLK = K/RC
C = 10pF
TA = 25°C
VS = ±7.5V
VS = ±5V
VS = ±2.5V
1.0 1.5 2.0 2.5 3.0
CLOCK FREQUENCY (MHz)
1065 F06
Figure 6. fCLK vs K
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.5
fCLK = K/RC
C = 10pF
TA = 70°C
VS = ±7.5V
VS = ±5V
VS = ±2.5V
1.0 1.5 2.0 2.5 3.0
CLOCK FREQUENCY (MHz)
1065 F07
Figure 7. fCLK vs K
LTC1065
A 4pF parasitic capacitance is assumed in parallel with the
external 10pF capacitor. A ±1% clock frequency variation
from device to device can be expected. The 2MHz clock
frequency designed above will typically drift to 1.74MHz at
70°C (Figure 7).
The internal clock of the LTC1065 can be overridden by an
external clock provided that the external clock source can
drive the timing capacitor C, which is connected from the
clock input pin to ground.
Output Offset
The DC output offset of the LTC1065 is trimmed to
typically less than ±1mV. The trimming is done at VS =
±5V. To obtain optimum DC offset performance, appropri-
ate PC layout techniques should be used and the filter IC
should be soldered to the PC board. A socket will degrade
the output DC offset by typically 1mV. The output DC offset
is sensitive to the coupling of the clock output pin 4 (N
package) to the negative power supply pin 3 (N package).
The negative supply pin should be well decoupled. When
the surface mount package is used, all NC pins should be
grounded. When the output DC voltage is measured with
a voltmeter, the filter output pin should be buffered. Long
test leads should be avoided.
With fixed power supplies, the output DC offset should not
change by more than ±100µV over 10Hz to 1MHz clock
frequency variation. When the filter clock frequency is
fixed, the output DC offset will typically change by – 4mV
(2mV) when the power supply varies from ±5V to ±7.5V
(±2.5V). See Typical Performance Characteristics.
Common Mode Rejection
The common mode rejection is defined as the change of
the output DC offset with respect to the DC change of the
input voltage applied to the filter.
CMR = 20log (∆VOS OUT/∆VIN)(dB)
Table 3 illustrates the common mode rejection for three
power supplies and three temperatures. The common
mode rejection improves if the output offset is adjusted to
approximately 0V. The output offset can be adjusted via
pin 8 (N package). See Typical Applications.
1065fb
9
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