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USB2503A

Integrated USB 2.0 Compatible 3-Port Hub

SMSC -> Microchip 

NAME

Crystal Output

Clock Input

Enable

RESET Input

Self-Power /

Bus-Power

Detect

TEST Pins

Analog Test

&

Internal 1.8V

voltage

regulator

enable

Integrated USB 2.0 Compatible 3-Port Hub

Datasheet

Table 4.3 Miscellaneous Pins (continued)

SYMBOL

XTAL2

CLKIN_EN

RESET_N

SELF_PWR

TEST[1:0]

ATEST/

REG_EN

TYPE

OCLKx

I

IS

I

IPD

AIO

FUNCTION

24MHz Crystal

This is the other terminal of the crystal, or left

unconnected when an external clock source is used to

drive XTAL1/CLKIN. It must not be used to drive any

external circuitry other than the crystal circuit.

Clock In Enable:

Low = XTAL1 and XTAL2 pins configured for use with

external crystal

High = XTAL1 pin configured as CLKIN, and must be

driven by an external CMOS clock.

This active low signal is used by the system to reset the

chip. The minimum active low pulse is 100ns.

Detects availability of local self-power source.

Low = Self/local power source is NOT available (i.e., 7-

Port Hub gets all power from Upstream USB VBus).

High = Self/local power source is available.

Used for testing the chip. User must treat as a no-

connect or connect to ground. For board testing, all

signal pins are included in an XNOR chain, Please see

Chapter 6, "XNOR Test," on page 37 for more details on

the configuration and use of the XNOR mode.

This signal is used for testing the analog section of the

chip, and to enable or disable the internal 1.8v regulator.

This pin must be connected to VDDA3P3 to enable the

internal 1.8V regulator, or to VSS to disable the internal

regulator.

When the internal regulator is enabled, the 1.8V power

pins must be left unconnected, except for the required

bypass capacitors.When the PHY is in test mode, the

internal regulator is disabled and the ATEST pin

functions as a test pin.

NAME

VDD1P8

VDDPLL1P8

VDDAPLL3P3

VDDA3P3

Table 4.4 Power, Ground, and No Connect

SYMBOL

VDD18

VDDA18PLL

VDDA33PLL

VDDA33

TYPE

FUNCTION

+1.8V core power.

If the internal regulator is enabled, then VDD18 pin

closest to VDD33CR must have a 4.7μF (or greater)

±20% (ESR <0.1Ω) capacitor to VSS

+1.8V Filtered analog power for internal PLL.

If the internal regulator is enabled, then this pin must

have a 4.7μF (or greater) ±20% (ESR <0.1Ω) capacitor

to VSS

+3.3V Filtered analog power for the internal PLL

If the internal PLL 1.8V regulator is enabled, then this pin

acts as the regulator input

+3.3V Filtered analog power.

Revision 2.3 (08-27-07)

12

DATASHEET

SMSC USB2503/USB2503A

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