VDS6632A4A Ver la hoja de datos (PDF) - A-Data Technology
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VDS6632A4A Datasheet PDF : 8 Pages
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V-Data
AC Characteristics
VDS6632A4A
Parameter
-5
-5.5
-6
Symbol
Unit Note
Min Max Min Max Min Max
System clock
Cycle time
/CAS Latency = 3 tCK3
/CAS Latency = 2 tCK2
5 1000 5.5
6
1000
1000 ns
10
10
10
Clock high pulse width
tCHW
2
- 2.25 -
2.5
-
ns
1
Clock low pulse width
tCLW
2
- 2.25 -
2.5
-
ns
1
Access time form /CAS Latency = 3 tAC3
clock
/CAS Latency = 2 tAC2
-
4.5
-
5
-
5.5
ns
2
-
6
-
6
-
6
Operation
/RAS cycle time
Auto Refresh
tRC
tRRC
55
-
55
-
60
-
ns
55
-
55
-
60
-
/RAS to /CAS delay
tRCD
15
- 16.5 -
18
-
ns
/RAS active time
tRAS
40 100K 38.5 100K 42 100K ns
/RAS precharge time
tRP
15
- 16.5 -
18
-
ns
/RAS to /RAS bank active delay
tRRD
10
-
11
-
12
-
ns
/CAS to /CAS delay
tCCD
1
-
1
-
1
-
CLK
Write command to data – in delay tWTL
0
-
0
-
0
-
CLK
Data – in to precharge command tDPL
1
-
1
-
1
-
CLK
Data – in active command
tDAL
5
-
5
-
5
-
CLK
DQM to data – out Hi-Z
tDQZ
2
-
2
-
2
-
CLK
DQM to data – in mask
tDQM
0
-
0
-
0
-
CLK
Data – out hold time
tOH
1.5
-
2
-
2
-
ns
Data – input setup time
tDS
1.5
-
1.5
-
1.5
-
ns
1
Data – input hold time
tDH
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
ns
1
Address hold time
tAH
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
ns
1
CKE hold time
tCKH
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
ns
1
Command hold time
tCH
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
ns
MRS to new command
tMRD
2
-
2
-
2
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
CLK
3
Refresh time
tREF
-
64
-
64
-
64
ms
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 April, 2001
6
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