LX1668 Ver la hoja de datos (PDF) - Microsemi Corporation
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LX1668 Datasheet PDF : 15 Pages
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PRODUCT DATABOOK 1996/1997
P ROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
PR O D U C T I O N D ATA S H E E T
LX1668
LINEAR REGULATOR (continued)
3.3V/5V
LX1668
LDRV 6
LFB 7
LIN EN
10k
10k
2N2222
APPLICATION INFORMATION
C5
330µF
Q4
IRLZ44
Supply Voltage
For I/O Chipset
R1
C7
330µF
R2
LAYOUT GUIDELINES - THERMAL DESIGN (continued)
Power Traces
To reduce power losses due to ohmic resistance, careful consid-
eration should be given to the layout of traces that carry high
currents. The main paths to consider are:
s Input power from 5V supply to drain of top MOSFET.
s Trace between top MOSFET and lower MOSFET or Schottky
diode.
s Trace between lower MOSFET or Schottky diode and ground.
s Trace between source of top MOSFET and inductor, sense
resistor and load.
s Current traces on both LDO sections
3.3V
Input
3.3V / 5V
Input
5V Input
FIGURE 11 — Enabling Linear Regulator
LAYOUT GUIDELINES - THERMAL DESIGN
A great deal of time and effort were spent optimizing the thermal
design of the demonstration boards. Any user who intends to
implement an embedded motherboard would be well advised to
carefully read and follow these guidelines. If the FET switches
have been carefully selected, external heatsinking is generally not
required. However, this means that copper trace on the PC board
must now be used. This is a potential trouble spot; as much
copper area as possible must be dedicated to heatsinking the FET
switches, and the diode as well if a non-synchronous solution is
used.
In our demonstration board, heatsink area was taken from
internal ground and VCC planes which were actually split and
connected with VIAS to the power device tabs. The TO-220 and
TO-263 cases are well suited for this application, and are the
preferred packages. Remember to remove any conformal coating
from all exposed PC traces which are involved in heatsinking.
General Notes
As always, be sure to provide local capacitive decoupling close to
the chip. Be sure use ground plane construction for all high-
frequency work. Use low ESR capacitors where justified, but be
alert for damping and ringing problems. High-frequency designs
demand careful routing and layout, and may require several
iterations to achieve desired performance levels.
VOUT2
VOUT3
VCC3
LX166x
PGND
Output
FIGURE 12 — Power Traces
All of these traces should be made as wide and thick as
possible, in order to minimize resistance and hence power losses.
It is also recommended that, whenever possible, the ground, input
and output power signals should be on separate planes (PCB
layers). See Figure 12 – bold traces are power traces.
Input Decoupling Capacitors
Ensure that capacitors C8 and C3 are placed as close to the IC as
possible to minimize the effects of noise on the device.
Layout Assistance
Please contact Linfinity’s Applications Engineers for assistance
with any layout or component selection issues. A Gerber file with
layout for the most popular devices is available upon request.
Evaluation boards are also available upon request. Please
check Linfinity's web site for further application notes.
Copyright © 1999
Rev. 1.0 4/99
Pentium is a registered trademark of Intel Corporation.
PRODUCTION DATA - Information contained in this document is proprietary to Lin Finity, and is current as of publication date. This document
may not be modified in any way without the express written consent of LinFinity. Product processing does not necessarily include testing of
all parameters. Linfinity reserves the right to change the configuration and performance of the product and to discontinue product at any time.
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