VSC837 Ver la hoja de datos (PDF) - Vitesse Semiconductor
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VSC837 Datasheet PDF : 26 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC837
3.2Gb/s
68x68 Crosspoint Switch
AC Characteristics
Table 1: Data Path
Symbol
Parameter
Min Typ Max Units
fRATE
Maximum Data Rate
— — 3.2 Gb/s
tSKW
Channel-to-channel delay skew
— 300 — ps
tPDAY
Propagation Delay from an A input to a Y output
— 750 — ps
tR, tF
High-speed input rise/fall times, 20% to 80%
— — 150 ps
tR, tF
tJR
tJP
High-speed output rise/fall times, 20% to 80%
Output added delay jitter, rms(1, 2)
Output added delay jitter, peak-to-peak(1, 2)
— — 150 ps
— — 10 ps
— — 40 ps
NOTES:(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 223-1 PRBS data pattern.
Table 2: Program Interface Timing
Symbol
Parameter
Min Typ Max Units
tsWRB
Setup time from INCHAN[6:0] or OUTCHAN[6:0] to rising edge of WRB
3.35 — — ns
thWRB
Hold time from rising edge of WRB to INCHAN[6:0] or OUTCHAN[6:0]
1.45 — — ns
tpwLW
Pulse width (HIGH or LOW) on LOAD
6.75 — — ns
tsCSB
Setup time from CSB to falling edge of LOAD or ALE_SCN in parallel or burst
mode, or rising edge of LOAD in serial mode.
0
——
ns
thCSB
Hold time of CSB rising edge after LOAD or ALE_SCN rising in parallel or
burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG 0
——
ns
in any mode.
tpwCFG Pulse width (HIGH or LOW) on CONFIG
6.75 — — ns
tsSDIN
Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising
1.65 — — ns
thSDIN
Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising
1.0 — — ns
tperSCLK Minimum period of SCLK in serial mode
15 — — ns
tsLOAD Setup time from LOAD to INCHAN1_SCLK rising
1.85 — — ns
thLOAD Hold time of LOAD after INCHAN1_SCLK rising
0.95 — — ns
Setup time from SERIAL rising to INCHAN1_SCLK rising when entering serial
tsSERIAL mode or SERIAL falling to LOAD falling when entering parallel mode or
SERIAL falling to LOAD rising when entering burst mode.
0.90 — — ns
thSERIAL
Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting serial
mode.
0
——
ns
tsBURST
Setup time from BURST rising to LOAD rising when entering burst mode or
BURST falling to LOAD falling when entering parallel mode.
1.85 — — ns
thBURST
tdsDOUT
tpwINITB
tsSCAN
Hold time from LOAD rising to BURST falling when exiting burst mode.
Delay from INCHAN1_SCLK rising to SDOUT, 20pF load.
Pulse width (HIGH or LOW) on INITB
Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
2.45 — — ns
— — 6.20 ns
6.75 — — ns
1.65 — — ns
thSCAN
Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
1.0 — — ns
G52309-0, Rev 3.0
02/16/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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