W133 Ver la hoja de datos (PDF) - Cypress Semiconductor

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W133

Spread Spectrum System Frequency Synthesizer

Cypress Semiconductor 

PRELIMINARY

Timing Diagrams (continued)

PCI_STOP# Timing Diagram[17, 18, 22, 23, 24, 25]

CPU

PCI

(internal)

PCI_STOP#

CPU_STOP#

HI

PWRDWN#

HI

PCI_F

(external)

PCI

(external)

PWRDWN# Timing Diagram[17, 22, 26, 27]

CPU

(internal)

PCI

(internal)

PWRDWN#

CPU

(external)

PCI

(external)

VCO

Crystal

Notes:

23. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.

24. All other clocks continue to run undisturbed.

25. PWRDWN# and CPU_STOP# are shown in a HIGH state.

26. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.

27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is required to be synchronized.

28. The shaded sections on the VCO and the Crystal signals indicate an active clock.

W133

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