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W150 Datasheet PDF : 15 Pages
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PRELIMINARY
W150
Table 4. Byte Writing Sequence (continued)
Byte
Sequence Byte Name
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
Bit Sequence
Byte Description
Refer to Table 5 The data bits in Data Bytes 0–5 set internal W150 registers that control device
operation. The data bits are only accepted when the Address Byte bit sequence is
11010010, as noted above. For description of bit control functions, refer to Table 5,
Data Byte Serial Configuration Map.
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6 Don’t Care
Unused by the W150, therefore bit values are ignored (Don’t Care).
11 Data Byte 7
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–5 Serial Configuration Map
Affected Pin
Bit(s) Pin No. Pin Name
Control Function
Bit Control
0
1
Default
Data Byte 0
7
–
6
–
–
(Reserved)
–
SEL_2
–
–
0
See Table 6
0
5
–
4
–
–
SEL_1
–
SEL_0
See Table 6
0
See Table 6
0
3
–
2
–
–
Frequency Table Selection
Frequency
Frequency
0
Controlled by FS Controlled by SEL
(3:0) Table 2
(3:0) Table 6
–
SEL3
Refer to Table 6
0
1–0
–
–
Bit 1 Bit 0 Function (See Table 7 for function details)
00
0
0 Normal Operation
0
1 (Reserved)
1
0 Spread Spectrum On
1
1 All Outputs Three-stated
Data Byte 1
7
–
–
–
–
–
0
6
–
5
–
4
–
–
–
–
–
–
–
–
–
0
–
–
0
–
–
0
3
46
SDRAM_F Clock Output Disable
2
49
CPU2
Clock Output Disable
1
51
CPU1
Clock Output Disable
Low
Active
1
Low
Active
1
Low
Active
1
0
52
Data Byte 2
7
–
CPU_F Clock Output Disable
–
(Reserved)
Low
Active
1
–
–
0
6
8
5
16
PCI_F
PCI5
Clock Output Disable
Clock Output Disable
Low
Active
1
Low
Active
1
Document #: 38-07177 Rev. *B
Page 6 of 15
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