W183 Ver la hoja de datos (PDF) - Cypress Semiconductor
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W183 Datasheet PDF : 9 Pages
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W183
Full Feature Peak Reducing EMI Solution
Features
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the out-
put
• Selectable output frequency range
• Single 1.25%, 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ...........................................VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz
Crystal Reference Range:................. 28 MHz ≤ Fin ≤ 40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Table 1. Modulation Width Selection
SS%
0
1
W183
Output
Fin ≥ Fout ≥ Fin –
1.25%
Fin ≥ Fout ≥ Fin –
3.75%
W183-5
Output
Fin + 0.625% ≥ Fin≥
– 0.625%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
0
0
0
1
1
0
1
1
Frequency Range
28 MHz ≤ FIN ≤ 38 MHz
38 MHz ≤ FIN ≤ 48 MHz
46 MHz ≤ FIN ≤ 60 MHz
58 MHz ≤ FIN ≤ 75 MHz
Pin Configuration
SOIC
XTAL
Input
40 MHz
Max
X1
X2
W183
Spread Spectrum
Output
(EMI suppressed)
FS2 1
CLKIN or X1 2
NC or X2 3
GND 4
GND 5
SS% 6
FS1 7
14 REFOUT
13 OE#
12 SSON#
11 Reset
10 VDD
9 VDD
8 CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W183
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07158 Rev. *A
Revised September 25, 2001
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