W25P240A Ver la hoja de datos (PDF) - Winbond

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W25P240A

64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Winbond 

Timing Waveforms, continued

Write Cycle Timing

W25P240A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[8:1]

CE

Single Write

TADSS

TADSH

Burst Write

TCYC

Write

Unselected

TKH TKL

ADSP is blocked by CE inactive

TADCS TADCH

TADVS

TADVH

ADSC initiated write

TAS TAH ADV must be inactive for ADSP write

WR1

WR2

TWS TWH

WR3

GW allows processor address (and BE = BWE)

to be pipelined during a writeback

TWS TWH

TWS TWH

TCES

WR1

TCEH

WR2

WR3

CE masks ADSP

Unselected with CE

OE

Data-Out

High-Z

Data-In

High-Z

TDS TDH

1a

DON'T CARE

UNDEFINED

BW[8:1] are applied only to first cycle of WR2

2a

2b

2c

2d

3a

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