W83195BG-118 Ver la hoja de datos (PDF) - Winbond
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W83195BG-118 Datasheet PDF : 28 Pages
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W83195BR-118/W83195BG-118
STEPLESS FOR INTEL 915/945 CHIPSETS
7.6 Register 5: Watchdog Control (Default: 02h)
BIT
NAME
PWD
DESCRIPTION
TYPE
7
SEL24_48 X 24_ 48 MHz output selection, 1: 24 MHz, 0: 48 MHz (Default). R/W
Default value follow hardware trapping data on SEL24_48# pin.
6
EN_WD
0 Program this bit =>
R/W
1: Enable Watchdog Timer feature.
0: Disable Watchdog Timer feature.
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
5 WD_TIMEOUT 0 Read Back only. Timeout Flag. This bit is Read Only.
R
1: Watchdog has ever started and counts to zero.
0: Watchdog is restarted and counting.
4 SAF_FREQ [4] 0
R/W
3 SAF_FREQ [3] 0
2
SAF_FREQ [2]
0
These bits will be reloaded in Reg-0 to select frequency table.
As the watchdog is timeout and EN_SAFE_FREQ=1.
1 SAF_FREQ [1] 1
0 SAF_FREQ [0] 0
7.7 Register 6: SRC, PCIE Control (1 = Enable, 0 = Stopped) (Default: FEh)
BIT
NAME
PWD
DESCRIPTION
7
26,27
1 SRCT/C output control
6
Reserved
1 Reserved
5
33,32
1 PCIET4/C4 output control
4
31,30
1 PCIET3/C3 output control
3
23,24
1 PCIET2/C2 output control
2
21,22
1 PCIET1/C1 output control
1
17,18
1 PCIET0/C0 output control
0
Reserved
0 Reserved
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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