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W83627SF

WINBOND I/O

Winbond 

W83627SF

4. PIN DESCRIPTION

Note: Please refer to Section 16.2 DC CHARACTERISTICS for details.

I/O8t - TTL level bi-directional pin with 8 mA source-sink capability

I/O12t - TTL level bi-directional pin with 12 mA source-sink capability

I/O12tp3 - 3.3V TTL level bi-directional pin with 12 mA source-sink capability

I/OD12t - TTL level bi-directional pin open drain output with 12 mA sink capability

I/OD16t - TTL level bi-directional pin open drain output with 16 mA sink capability

I/OD24 - TTL level bi-directional pin open drain output with 24A sink capability

OUT2 - Output pin with 2 mA source-sink capability

OUT12 - Output pin with 12 mA source-sink capability

O12tp3 - 3.3V output pin with 12 mA source-sink capability

OD12 - Open-drain output pin with 12 mA sink capability

OD24 - Open-drain output pin with 24 mA sink capability

INcs - CMOS level Schmitt-trigger input pin

INt

- TTL level input pin

INtd - TTL level input pin with internal pull down resistor

INts - TTL level Schmitt-trigger input pin

INtsp3 - 3.3V TTL level Schmitt-trigger input pin

4.1 LPC Interface

SYMBOL

CLKIN

PME#

PCICLK

LDRQ#

SERIRQ

LAD[3:0]

LFRAME#

LRESET#

SUSCLKIN

PIN

18

19

21

22

23

24-27

29

30

75

I/O

INt

OD12

INtsp3

O12tp3

I/OD12t

I/O12tp3

INtsp3

INtsp3

INts

FUNCTION

System clock input. According to the input frequency 24MHz or

48MHz, it is selectable through register. Default is 24MHz input.

Generated PME event.

PCI clock input.

Encoded DMA Request signal.

Serial IRQ input/Output.

These signal lines communicate address, control, and data

information over the LPC bus between a host and a peripheral.

Indicates start of a new cycle or termination of a broken cycle.

Reset signal. It can connect to PCIRST# signal on the host.

32khz clock input, for CIR only.

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Publication Release Date: May 31, 2005

Revision A1

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