WPCN385L Ver la hoja de datos (PDF) - Winbond

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WPCN385L

LPC-to-LPC Switch, Fast Infrared Port, Serial Port and GPIOs

Winbond 

Features

■ Docking LPC Switch

— Hot plugability

— LPCPD and CLKRUN support

— The connection is controlled by software

— Low switch resistance and propagation delay

— Programmable Clock to Reset Delay

■ Fast Infrared Port (FIR)

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— FIR IrDA 1.1 compliant

— HP-SIR

— ASK-IR option of SHARP-IR

— DASK-IR option of SHARP-IR

— Consumer Remote Control supports RC-5, RC-6,

NEC, RCA and RECS 80

— DMA support: one or two channels

■ Serial Port (SP)

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— UART data rates up to 1.5 Mbaud

■ 18 General-Purpose I/O (GPIO) Ports

— Supports IRQ assertion

— Programmable drive type for each output pin (open-

drain, push-pull or output disable)

— Programmable option for internal pull-up resistor on

each input pin

— Output lock option

— Input debounce mechanism

■ LPC System Interface

— 8-bit I/O cycles

— LPCPD and CLKRUN support

— Implements PCI mobile design guide recommenda-

tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)

■ PC2001 and ACPI 3.0 Compliant

— PnP Configuration Register structure

— Flexible resource allocation for all logical devices

❏ Relocatable base address

❏ 15 IRQ routing options

❏ Optional 8-bit DMA channels (where applicable)

selected from four possible DMA channels

■ Clock Sources

— 14.318 MHz or 48 MHz clock input

— LPC clock, 0 or 30 MHz to 33 MHz

— 14.318 MHz or 48 MHz clock output to the docking

station

■ Strap Configuration

— Base Address (BADDR) strap to determine the base

address of the Index-Data register pair

— Docking LPC disable (DLPC_DIS) strap to control

the LPC-to-LPC Switch

— Strap Inputs to select testability mode

■ Power Supply

— 3.3V supply operation

— All pins are 5V tolerant, except LPC bus pins

— All pins are back-drive protected, except LPC bus pins

■ Testability

— XOR Tree

— TRI-STATE device pins

Internal Block Diagram

14.31818 MHz

LPC Interface

Clock

Generator

Bus

Interface

Docking

LPC Switch

48 MHz

GPIO Ports

Serial Port

FIR Port

Ports

I/O

Serial

Interface

FIR

Interface

Docking LPC

Interface

www.winbond.com

2

Revision 1.0

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