W48S8704H(1999) Ver la hoja de datos (PDF) - Cypress Semiconductor

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W48S8704H
(Rev.:1999)

Spread Spectrum 3 DIMM Desktop Clock

Cypress Semiconductor 

PRELIMINARY

W48S87-04

How To Use the Serial Data Interface

Electrical Requirements

Figure 5 illustrates electrical characteristics for the serial inter-

face bus used with the W48S87-04. Devices send data over

the bus with an open drain logic output that can (a) pull the bus

line LOW, or (b) let the bus default to logic 1. The pull-up resis-

tors on the bus (both clock and data lines) establish a default

logic 1. All bus devices generally have logic inputs to receive

data.

Although the W48S87-04 is a receive-only device (no data

write-back capability), it does transmit an “acknowledge” data

pulse after each byte is received. Thus, the SDATA line can

both transmit and receive data.

The pull-up resistor should be sized to meet the rise and fall

times specified in AC parameters, taking into consideration to-

tal bus line capacitance.

VDD

VDD

SERIAL BUS DATA LINE

SERIAL BUS CLOCK LINE

CLOCK IN

CLOCK OUT

SDCLK

DATA IN

N DATA OUT

~ 2kΩ

~ 2kΩ

SDATA

N

CLOCK IN

SCLOCK

DATA IN

DATA OUT

SDATA

N

CHIP SET

(SERIAL BUS MASTER TRANSMITTER)

CLOCK DEVICE

(SERIAL BUS SLAVE RECEIVER)

Figure 5. Serial Interface Bus Electrical Characteristics

11

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