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CS8401A-CP

Digital Audio Interface Transmitter

Cirrus Logic 

CS8401A

channel status data cyclic redundancy check

characters are generated independently for chan-

nels A and B and are transmitted at the end of the

channel status block. When MUTE (bit 1) is low,

the transmitted audio data is forced to zero. Both

RST and MUTE are set to zero upon power up.

When RST is low, the differential line drivers are

set to ground and the block counters are reset to the

beginning of the first block. In order to properly

synchronize the rest of the CS8401A to the audio

serial port, the transmit timing counters, which in-

clude the flags in the status register, are not enabled

after RST is set high until eight and one half SCK

periods after the active edge (first edge after reset is

exited) of FSYNC.

When FSYNC is configured as a left/right signal

(FSF1 = 1), the counters and flags are not en-

abled until the right sample is being entered

(during which the previous left sample is being

transmitted). This guarantees that channel A is

left and Channel B is right as per the digital

audio interface specs.

Control register 3 contains format information for

the serial audio input channel. The MSB is unused

and the next three bits, SDF2-SDF0, select the for-

mat for the serial input data with respect to

FSYNC. There are five valid combinations of these

bits as shown in Figure 10. The next two bits,

FSF1 and FSF0, select the format of FSYNC. Two

7

6

5

4

3

2

1

0

X:03

SDF2 SDF1 SDF0 FSF1 FSF0 MSTR SCED

SDF2: with SDF0 & SDF1, select serial data format.

SDF1: with SDF0 & SDF2, select serial data format.

SDF0: with SDF1 & SDF2, select serial data format.

FSF1: with FSF0, select FSYNC format.

FSF0: with FSF1, select FSYNC format.

MSTR: When set, SCK and FSYNC are outputs.

SCED: When set, rising edge of SCK latches data.

When clear, falling edge of SCK latches data.

Figure 9. Control Register 3

10

of the formats delineate each channel’s data and

do not indicate the particular channel. The other

two formats also indicate the specific channel.

The formats are shown in Figure 10. Bit 1,

MSTR, determines whether FSYNC and SCK

are inputs, MSTR low, or outputs, MSTR high.

Bit 0, serial clock edge select, SCED, selects the

edge that audio data gets latched on. When

SCED is low, the falling edge of SCK latches

data in the chip and when SCED is high, the ris-

ing edge is used.

The multitude of combinations allow for a zero

glue logic interface to almost all DSP’s, encoder

chips, and standard serial data formats.

Serial Port

The serial port is used to enter audio data and

consists of three pins: SCK, SDATA, and

FSYNC. The serial port is double buffered with

SCK clocking in the data from SDATA, and

FSYNC delineating audio samples and may de-

fine the particular channel, left or right.

Control register 3, shown in Figure 9, configures

the serial port. All the various formats are illus-

trated in Figure 10. When FSF1 is low, FSYNC

only delineates audio samples. When FSF1 is

high, it delineates audio samples and specifies

the channel. When FSF1 is low and the port is a

master (MSTR = 1), FSYNC is a square wave

output. When FSF1 is low and the port is a slave

(input), FSYNC can be a square wave or a pulse

provided the active edge, as defined in Fig-

ure 10, is properly positioned with respect to

SDATA.

Bits 4, 5, and 6, SDF0-SDF2, define the format

of SDATA and is also described in Figure 10.

The five allowable formats are MSB first, MSB

last, 16-bit LSB last, 18-bit LSB last, and 20-bit

LSB last. The MSB first and MSB last formats

accept any word length from 16 to 24 bits. The

word length is controlled by providing trailing

zeros in MSB first mode and leading zeros in

DS60F1

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