CS8402A-IP Ver la hoja de datos (PDF) - Cirrus Logic
Número de pieza
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CS8402A-IP Datasheet PDF : 34 Pages
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CS8401A
SDF
210 (bit)
000
Name
MSB First
001
MSB Last
010
LSB Last 16
100
LSB Last 18
110
LSB Last 20
FSF MSTR
10 (bit)
00
0 FSYNC Input
01
0 FSYNC Input
10
0 FSYNC Input
11
0 FSYNC Input
Left Sample
Right Sample
MSB 24 bits, incl. Aux
LSB
MSB 24 bits, incl. Aux
LSB
MSB
MSB
LSB 24 bits, incl. Aux
MSB
LSB 24 bits, incl. Aux
MSB
16 Bits
16 Bits
LSB
MSB
LSB
MSB
LSB
18 Bits
18 Bits
LSB
MSB
LSB
MSB
LSB
20 Bits
20 Bits
LSB
MSB
LSB
MSB
LSB
00
1 FSYNC Output
01
1 FSYNC Output
10
1 FSYNC Output
11
1 FSYNC Output
16 Clocks
16 Clocks
32 Clocks
32 Clocks
16 Clocks
16 Clocks
32 Clocks
32 Clocks
Figure 10. CS8401A Serial Port SDATA and FSYNC Timing
MSB last mode, or by restricting the number of
SCK periods between samples to the sample
word length. The 16-, 18-, and 20-bit LSB-last
modes require at least 16, 18, or 20 SCK periods
per sample respectively. As a master, 32 SCK pe-
riods are output per sample.
FSYNC must be derived from MCK via a DSP
using the same clock or by external counters. If
FSYNC moves (jitters) with respect to MCK by
more than 4 MCK periods, the CS8401A may
reset the channel status block and flags. Appen-
dix C contains more information on the
relationship of FSYNC and MCK.
Buffer Memory
In all buffer modes, the status register and con-
trol registers are located at addresses 0-3
respectively, and the user data is buffered in lo-
cations 4-7. The parallel port can access any
location in the user data buffer at any time; how-
ever, care must be taken not to modify a location
when that location is being read internally. This
internal reading is done through the second port
of the buffer and is done in a cyclic manner.
Reset initializes the internal pointer to
04H (Hex). Data is read from this location and
stored in an 8-bit shift register which is shifted
once per audio sample. (An audio sample is de-
fined as a single channel, not a stereo pair.) The
byte is transmitted LSB first, D0 being the first
bit. After transmitting 8 samples, i.e. 8 user bits,
the address pointer is incremented and the next
byte of user data is loaded into the shift register.
After transmitting all four bytes, 32 audio sam-
DS60F1
11
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