CS8402A-CS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8402A-CS Datasheet PDF : 34 Pages
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CS8401A
Flag 2
Flag 1
Flag 0
C.S. Byte
Left C.S. Ad.
Right C.S. Ad.
Block
(384 Audio Samples)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1
08
0B 0C
0F 0C
0F 0C
0F 0C
0F 0C
0F 08
10
13 14
17 14
17 14
17 14
17 14
14 10
(Expanded)
(Addresses are in Hex)
Flag 1
Flag 0
Left C.S. Ad.
Right C.S. Ad.
User Address
08
09
0A
0B
10
11
12
13
04 05 06 07 04 05 06 07
Figure 14. CS8401A Buffer Memory Read Sequence - MODE 2
Buffer-Read and Interrupt Timing
As mentioned previously in the buffer mode sec-
tions, conflicts between externally writing to the
buffer ram and the CS8401A internally reading
bytes of ram for transmission may be averted by
using the flag levels to avoid the section cur-
rently being addressed by the part. Interrupts
occur at flag edges indicating the exact byte that
the part is currently reading. Utilizing INT along
with the flags, the byte currently being read by the
part can be avoided allowing access to all other
bytes instead of just a section. Figure 15 illustrates
the timing between flags, INT, and the internal
reading of the buffer for transmission. The mas-
ter clock IMCK is shown as 128×Fs. Other
MCK frequencies are initially divided to obtain
128×Fs, defined as IMCK (internal MCK),
which is then used for all internal timing, so the
timing in Figure 15 is valid for all MCK fre-
quencies. When the parity bit (P) is transmitted, a
transition on a flag causes INT to go low if the
appropriate mask bit is set. Concurrently, the part
starts reading from the internal buffer. Writing to
the buffer ram location being read by the part
should be avoided while the internal "ram read"
signal is high.
IMCK (128Fs)
Flags 0 & 1
Flag 2
INT
RAM Read
TXP
C
P
TXN
Transmit Preamble
Figure 15. RAM/Buffer-Read and Interrupt Timing
DS60F1
15
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