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SAA7191B

Digital multistandard colour decoder, square pixel (DMSD-SQP).

Philips Electronics 

Philips Semiconductors

Digital Multistandard Colour Decoder,

Square Pixel (DMSD-SQP)

Product specification

SAA7191B

6 PINNING

SYMBOL

SP

AP

RESN

CREF

VDD1

CHR0

CHR1

CHR2

CHR3

CHR4

CHR5

CHR6

CHR7

CVBS0

CVBS1

CVBS2

CVBS3

VDD2

VSS1

CVBS4

CVBS5

CVBS6

CVBS7

GPSW1

GPSW2

HCL

LLC

VDD3

HSY

VS

HS

HL

XTAL

XTALI

VSSA

LFCO

VDDA

VSS2

ODD

SDA

PIN

DESCRIPTION

1 connected to ground (shift pin for testing)

2 connected to ground (action pin for testing)

3 reset, active LOW

4 clock reference, sync from external to ensure in-phase signals on the YUV-bus

5 +5 V supply input 1

6

7

8

9 chrominance input data bits CHR7 to CHR0

10 from a Y/C (VHS, Hi8) source in two’s complement format

11

12

13

14

15 luminance respectively CVBS lower input data bits CVBS3 to CVBS0

16 (CVBS with luminance, chrominance and all sync information in two’s complement format)

17

18 +5 V supply input 2

19 ground 1 (0 V)

20

21 luminance respectively CVBS upper input data bits CVBS7 to CVBS4

22 (CVBS with luminance, chrominance and all sync information in two’s complement format)

23

24 Port 1 output for general purpose (programmable)

25 Port 2 output for general purpose (programmable)

26 black level clamp pulse (programmable), e.g. for TDA8708 (ADC)

27 line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system)

28 +5 V supply input 3

29 horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC)

30 vertical sync output signal

31 horizontal sync output signal (programmable)

32 horizontal lock flag, HIGH = PLL locked

33 26.8 MHz clock output

34 26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave)

35 analog ground

36 line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz)

37 +5 V supply input for analog part

38 ground 2 (0 V)

39 odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1

40 I2C-bus data line

August 1996

5

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