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CXD1915R

Digital Video Encoder

Sony Semiconductor 

CXD1915R

Pin

No.

Symbol I/O

Description

17 VSYNC

Vertical sync signal input/output.

I/O

When SYNCM (Pin 72) = High, this pin is the vertical sync signal output.

When SYNCM = Low, this pin is the vertical sync signal input, and the falling

edge is detected during the 1st field to reset the internal circuits.

18 HSYNC

Horizontal sync signal input/output.

I/O

When SYNCM (Pin 72) = High, this pin is the horizontal sync signal output.

When SYNCM = Low, this pin is the horizontal sync signal input, and the falling

edge is detected during the 1st field to reset the internal circuits.

19 CSYNC

O Composite sync output when using RGB output.

20 BF

O

Burst flag output. The burst flag is synchronized with the composite video signal

(CP-OUT) and indicates its color burst signal position.

21 VSS5

— Digital ground.

22 PD0

23 PD1

24 PD2

25 PD3

I 8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is

I input. [PD0 to PD7]

When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr

I signal inputs. When control register bit "PIF MODE" = "1", these are Y signal

I inputs.

26 VDD2

— Digital power supply.

27 PD4

28 PD5

29 PD6

30 PD7

I 8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is

I input. [PD0 to PD7]

When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr

I signal inputs. When control register bit "PIF MODE" = "1", these are Y signal

I inputs.

31 VSS6

— Digital ground.

32 PD8/TD0 I/O Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]

33 PD9/TD1 I/O When control register bit "PIF MODE" = "0", these inputs are not used. When control

register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs.

34 PD10/TD2 I/O In test mode, these are used for the internal circuit test data bus. The test data

35 PD11/TD3 I/O bus is available only for the device vendor.

36 VSS7

— Digital ground.

37 PD12/TD4 I/O Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]

38 PD13/TD5 I/O When control register bit "PIF MODE" = "0", these inputs are not used. When control

register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs.

39 PD14/TD6 I/O In test mode, these are used for the internal circuit test data bus. The test data

40 PD15/TD7 I/O bus is available only for the device vendor.

41 VDD3

— Digital power supply.

42 NC

— Not connected inside the IC.

43 IREF

O

DAC reference current output.

Connect resistance "16R" which is 16 times output resistance "R".

44 VREF

I

DAC reference voltage input.

Sets the DAC output full-scale width.

45 CP-OUT O 10-bit DAC output. This pin outputs the composite signal.

–4–

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