YGV628B Ver la hoja de datos (PDF) - Yamaha Corporation

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YGV628B

Advanced Video Display Processor 7

Yamaha Corporation 

YGV628B

■ Pin Table

Pins Name Numbers I/O

Functions

CUP Interface

D15-0

16

I/O CPU Data Bus

A23-1

23

I CPU Address Bus

CS_N

1

I Chip Select

RD_N

1

I READ Pulse Input

WRH_N

1

I WRITE Strobe Input/D15-8

WRL_N

1

I WRITE Strobe Input/D7-0

WAIT_N

1

O CPU Bus WAIT (3-State Output)

READY_N

1

O CPU Bus Ready (3-State Output)

INT_N

1

O Interrupt

DREQ_N

1

O Direct Memory Access

RESET_N

1

I Reset Input

Video Memory Interface

SDQ15-0

16

I/O Video Memory Data Bus

SA13-0

14

O Video Memory Address Bus

SCS_N

1

RAS_N

1

CAS_N

1

WE_N

1

UDQM

1

LDQM

1

SDCKOUT

1

O Video Memory Chip Enable

O Video Memory Low Address Strobe Output

O

Video Memory Column Address Strobe

Output

O Video Memory WRITE Enable

O Video Memory Data Mask Output/ SDQ15-8

O Video Memory Data Mask Output/ SDQ7-0

O Video Memory Clock Output

Monitor Interface

R,G,B

3

O Analog R, G, B, Signals Output

IREF

1

- DAC Reference Electric-current Input

DRI5-0

6

I Digital R Signal Input

DGI5-0

6

I Digital G Signal Input

DBI5-0

HSIN_N

VSIN_N

6

I Digital B Signal Input

1

I Horizontal Synchronized Signal Input

1

I Vertical Synchronized Signal Input

YS_N

1

O YS Signal Output

DRO5-0

6

O Digital R Signal Output

DGO5-0

6

O Digital G Signal Output

DBO5-0

6

VSYNC_N

1

CSYNC_N

1

BLANK_N

1

O Digital B Signal Output

O Vertical Synchronized Signal Output

O

Horizontal Synchronized Signal / Compound

Synchronized Signal Output

O Non-display Interval Output

GCK1OUT

1

O Dot Clock Output 1

GCK2OUT

1

O Dot Clock Output 2

5Tr : 5V supply Yes/No Yes Æ ○ / No Æ ×

Drive：Driving Capability

Level 5Tr Drive

LVTTL ○ 4mA

LVTTL ○

LVTTL ○

LVTTL ○

LVTTL ○

LVTTL ○

LVTTL ○ 4mA

LVTTL ○ 4mA

LVTTL × 4mA

LVTTL × 4mA

LVCMOS ○

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

○ 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 8mA

Analog

Analog

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

×

×

○

○

○

○

○

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

× 4mA

-6-

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