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Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
T2
Tw
T3
Ø
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
T1
T2
E
(Example:
I/O Read -
Opcode
Fetch)
E
(I/O Write)
50
49
51
50
49
52
54
53
53
54
Figure 11. E Clock Timing
(Minimum timing example
of PWEL and PWEH)
Ø
TOUT
Timer Data
Reg = 0000H
55
Figure 12. Timer Output Timing
DS971890301
11