RTL8196C Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8196C Datasheet PDF : 44 Pages
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RTL8196C
Datasheet
5.1. RTL8196C Configuration Upon Power On Strapping
All mode configuration pins are internal pull low. The 1.0V digital core power input pin voltage is up to
0.7V on system power-on. The strap data will be latched after a delay of 300ms.
Table 2. RTL8196C Configuration Upon Power On Strapping
H/W Pin Name Configuration Name
Pin No Description
MA11, MA10,
MA9
ck_cpu_freq_sel[2:0]
56, 62, 55 CPU Clock Configuration
000: 250MHz
001: 270MHz
010: 290MHz
011: 310MHz
MA8, MA7, MA6 ck_freq_sel[2:0]
altekIAL MA5
Re ENT ION MA2
ID RAT MA1
NF RPO MA3
CO E CO MA4
for ZT MA12
Sync_lx_oc
EnOLTautoTestMode
BOOTSEL
Clklx_from_clkm
ENABLE_EXT_RSTN
ck_cpu_div_sel
53, 52, 51
50
59
60
58
49
57
100: 330MHz
101: 350MHz
110: 370MHz
111: 390MHz
SDRAM Clock Rate Configuration
000: 65.625MHz
001: 78.125MHz
010: 125MHz
011: 150MHz
100: 156.25MHz
101: 168.75MHz
110: 193.75MHz
111: Reserved
Selection for Internal Bus Test Mode
This is a hardware strapping pin.
0: Normal mode
1: Test mode
Enable Operational Level Test (OLT) Auto Test Mode
0: Normal mode
1: Test mode
Boot Device Select for Flash Booting
0: Boot from NOR-type Flash (default)
1: Boot from Serial Flash (SPI)
Internal Local Bus Source
0: 200MHz
1: From memory clock
External Reset
0: Disable chip RESET function; Pin 108 can be used as a
GPIO or DBG pin
1: Enable chip RESET function
PLL Clock for CPU
0: CPU PLL clock is not divided by 2
1: CPU PLL clock is divided by 2
MA13
en_router_mode
65
Router or AP Mode Select
0: AP mode (Turns-off Ethernet Switch and Port 0 to Port 3
PHY circuit for power-saving)
1: Router mode (All Ethernet Ports are working)
MA14
swap_dbg_halfword
63
Internal Debug Mode Select
IEEE 802.11n AP/Router Network Processor with EEE 9
Track ID: JATR-2265-11 Rev. 0.7
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