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RTL8196

IEEE 802.11n AP/ROUTER NETWORK PROCESSOR WITH EEE

Realtek Semiconductor 

RTL8196C

Datasheet

6.4.3. DRAM Timing Register (DTR) (0xB800_1008)

This register does not provide byte access.

Table 6. DRAM Timing Register (DTR) (0xB800_1008)

Bit Name

Description

Mode Default

31:29 T_RP

tRP Timing Parameter of DRAM

RW 111B

Basic unit = 1* DRAM_CLK

000 means 1 unit

28:26 T_RCD

tRCD Timing Parameter of DRAM

RW 111B

Basic unit = 1* DRAM_CLK

000 means 1 unit

25:21 T_RAS

20:16 T_RFC

k 15:12 T_REFI

alteTIAL 11:9 T_REFI_UNIT

Re IDENATION 8:6 T_WR

CforOZTNEFCORPOR 5:0 Reserved

Minimum T_RAS Timing Parameter of DRAM

Basic unit = 1* DRAM_CLK

00000 means 1 unit

tRFC Timing Parameter of DRAM

Refresh row cycle time

Basic unit = 1* DRAM_CLK

00000 means 1 unit

tREF Timing Parameter of DRAM

Refresh row interval time

Basic unit = T_REFI_UNIT

0000: 1 unit

0001: 2 units

…

1111: 16 units

Basic Unit of T_REFI

000: 32 DRAM_CLK

001: 64 DRAM_CLK

010: 128 DRAM_CLK

011: 256 DRAM_CLK

100: 512 DRAM_CLK

101: 1024 DRAM_CLK

110: 2048 DRAM_CLK

111: 4096 DRAM_CLK

tWR Timing Parameter of DRAM

Write recovery time

Basic unit = 1* DRAM_CLK

000 means 1 unit

Reserved

RW 11111B

RW 11111B

RW 0000B

RW 111B

RW 111B

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IEEE 802.11n AP/Router Network Processor with EEE 15

Track ID: JATR-2265-11 Rev. 0.7

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