RTL8196C-GR Ver la hoja de datos (PDF) - Realtek Semiconductor

Número de pieza

componentes Descripción

Lista de partido

RTL8196C-GR

IEEE 802.11n AP/ROUTER NETWORK PROCESSOR WITH EEE

Realtek Semiconductor 

RTL8196C

Datasheet

Table of Contents

1. GENERAL DESCRIPTION ..............................................................................................................................................1

2. FEATURES .........................................................................................................................................................................2

3. BLOCK DIAGRAM ...........................................................................................................................................................4

4. PIN ASSIGNMENTS .........................................................................................................................................................5

4.1. PIN ASSIGNMENTS .......................................................................................................................................................5

4.2. PACKAGE IDENTIFICATION...........................................................................................................................................5

5. PIN DESCRIPTIONS.........................................................................................................................................................6

5.1. RTL8196C CONFIGURATION UPON POWER ON STRAPPING ........................................................................................9

5.2. SHARED I/O PIN MAPPING .........................................................................................................................................10

6. MEMORY CONTROLLER ............................................................................................................................................11

6.1. SDRAM CONTROL INTERFACE..................................................................................................................................11

6.1.1. Features................................................................................................................................................................11

6.2. NOR FLASH TYPE MEMORY ......................................................................................................................................11

k 6.2.1. Features................................................................................................................................................................11

6.2.2. Bank Address Mapping.........................................................................................................................................12

lte 6.2.3. Flash Command Sequence....................................................................................................................................12

6.3. SPI FLASH CONTROLLER ...........................................................................................................................................13

6.3.1. Features................................................................................................................................................................13

L 6.4. SOFTWARE REGISTER DEFINITION .............................................................................................................................13

a IA 6.4.1. Memory Control Register (MCR) (0xB800_1000) ...............................................................................................13

6.4.2. DRAM Configuration Register (DCR) (0xB800_1004)........................................................................................14

6.4.3. DRAM Timing Register (DTR) (0xB800_1008)....................................................................................................15

T 6.4.4. NOR Flash Configuration Register (NFCR) (0xB800_1100)...............................................................................16

e N N 6.4.5. SPI Flash Configuration Register (SFCR) (0xB800_1200)..................................................................................16

R E IO 6.4.6. SPI Flash Configuration Register 2 (SFCR2) (0xB800_1204).............................................................................17

6.4.7. SPI Flash Control and Status Register (SFCSR) (0xB800_1208) ........................................................................18

T 6.4.8. SPI Flash Data Register (SFDR) (0xB800_120C) ...............................................................................................18

ID A 6.4.9. SPI Flash Data Register 2 (SFDR2) (0xB800_1210)...........................................................................................19

R 7. PERIPHERAL AND MISC CONTROL ........................................................................................................................20

NF PO 7.1. GPIO CONTROL .........................................................................................................................................................20

7.1.1. GPIO Register Set (0xB800_3500).......................................................................................................................20

R 7.1.2. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)............................................................20

O O 7.1.3. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800_3508)..........................................................20

C C 7.1.4. Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C) ..........................................................................21

E 7.1.5. Port A, B, C, D Interrupt Status Register (PABCD_ISR) (0xB800_3510) ...........................................................21

T 7.1.6. Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514) ..........................................................................21

7.1.7. Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518).........................................................................22

Z 7.2. GPIO SHARED PIN MAPPING LIST .............................................................................................................................22

for 8. GREEN ETHERNET.......................................................................................................................................................24

8.1. CABLE LENGTH POWER SAVING ................................................................................................................................24

8.2. LINK DOWN POWER SAVING......................................................................................................................................24

8.3. ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................24

9. DC SPECIFICATIONS....................................................................................................................................................25

9.1. OPERATING CONDITIONS ...........................................................................................................................................25

9.2. POWER DISSIPATION ..................................................................................................................................................25

IEEE 802.11n AP/Router Network Processor with EEE iii

Track ID: JATR-2265-11 Rev. 0.7

Share Link: