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IN74HC75D

Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS

Integral Corp. 

TECHNICAL DATA

Dual 2-Bit Transparent Latch

High-Performance Silicon-Gate CMOS

IN74HC75

The IN74HC75 is identical in pinout to the LS/ALS75. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device consists of two independent 2-bit transparent latches

and can be used as temporary storage for binary information between

processing units and input/output or indicator units. Each latch stores

the input data while Latch Enable is at a logic low. The outputs follow

the data inputs when Latch Enable is at a logic high.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

IN74HC75N Plastic

IN74HC75D SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

PIN 5=VCC

PIN 12 = GND

FUNCTION TABLE

Inputs

D

Latch

Enable

L

H

H

H

X

L

X = Don’t Care

Q0 = latched data

Outputs

QQ

LH

HL

Q0 Q0

89

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