72V275L10PF Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

fabricante

72V275L10PF

3.3 VOLT CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18

Integrated Device Technology 

IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM

32,768 x 18 and 65,536 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

72V275 (32,768 x 18_BIT)

17 15 14

0

EMPTY OFFSET REGISTER

DEFAULT VALUE

007FH if LD is LOW at Master Reset,

03FFH if LD is HIGH at Master Reset

17 15 14

0

FULL OFFSET REGISTER

DEFAULT VALUE

007FH if LD is LOW at Master Reset,

03FFH if LD is HIGH at Master Reset

72V285 (65,536 x 18_BIT)

17 16 15

0

EMPTY OFFSET REGISTER

DEFAULT VALUE

007FH if LD is LOW at Master Reset,

03FFH if LD is HIGH at Master Reset

17 16 15

0

FULL OFFSET REGISTER

DEFAULT VALUE

007FH if LD is LOW at Master Reset,

03FFH if LD is HIGH at Master Reset

4512 drw 06

Figure 3. Offset Register Location and Default Values

LD WEN REN SEN

00

1

1

WCLK

01

0

1

X

01

1

0

X1

1

1

X

RCLK

X

X

X

72V275

72V285

Parallel write to registers:

Empty Offset

Full Offset

Parallel read from registers:

Empty Offset

Full Offset

Serial shift into registers:

30 bits for the 72V275

32 bits for the 72V285

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

No Operation

10

X

X

X

Write Memory

1X

0

X

X

11

1

X

X

Read Memory

X

No Operation

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

4512 drw 07

Figure 4. Programmable Flag Offset Programming Sequence

9

Share Link: