SCC2692 Ver la hoja de datos (PDF) - Philips Electronics
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SCC2692 Datasheet PDF : 30 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC2692
AC CHARACTERISTICS (Continued)1, 2, 4
SYMBOL
Port Timing5 (See Figure 5)
PARAMETER
LIMITS
Min
Typ3
Max
UNIT
tPS
Port input setup time before RDN Low
tPH
Port input hold time after RDN High
tPD
OPn output valid from WRN High
Interrupt Timing (See Figure 6)
0
ns
0
ns
400
ns
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
tIR9
Reset command (break change interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
300
ns
300
ns
300
ns
300
ns
300
ns
300
ns
Clock Timing (See Figure 7)
tCLK
fCLK10
tCTC
fCTC8
tRX
fRX8
tTX
fTX8
X1/CLK High or Low time
X1/CLK frequency
CTCLK (IP2) High or Low time
CTCLK (IP2) frequency
RxC High or Low time
RxC frequency
(16X)
(1X)
TxC High or Low time
TxC frequency
(16X)
(1X)
100
0
3.6864
4
100
0
4
220
0
2
0
1
220
0
1
0
1
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
Transmitter Timing (See Figure 8)
tTXD
TxD output delay from TxC external clock input on IP pin
tTCS
Output delay from TxC low at OP pin to TxD data output
Receiver Timing (See Figure 9)
350
ns
0
150
ns
tRXS
RxD data setup time before RxC high at external clock input on IP pin
240
ns
tRXH
RxD data hold time after RxC high at external clock input on IP pin
200
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
7. Guaranteed by characterization of sample units.
8. Minimum frequencies are not tested but are guaranteed by design.
9. 325ns maximum for TA > 70°C.
10. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.
1998 Sep 04
7
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