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HD151011

Dual BCD Programmable Counter with Synchronous Preset Enable

Hitachi -> Renesas Electronics 

HD151011

Function Table

Control Inputs

CLR PR SPE C/T Mode

Operation Description

H

H

H

X

Generally count

Down count at the rise edge of clock (CLK),

Down count at the fall edge of clock (CLK)

X

X

L

X

Synchronous preset

Jn data is preset at the rise of clock (CLK),

the fall of clock (CLK)

—

—

—

H

—

Clock inputs (CLK, CLK) is CMOS level

—

—

—

L

—

Clock inputs (CLK, CLK) is TTL level

L

H

—

—

Initialize of Q output

Initialize of Q = "L"

H

L

—

—

Initialize of Q output

Initialize of Q = "H"

H: High level

L: Low level

Z: Immaterial

—: Irrespective of condition

1. Synchronous preset (SPE) input can set max 99 down counts.

2. When the count value is 0, the next clock pulse presets the data to invert the output.

3. CLR and PR inputs initialize output state.

4. Clock inputs (CLK, CLK) is selectable CMOS level (VCC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V)

(Jn, C/T, PR, CLR and SPE inputs are CMOS level)

Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)

2

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